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1. 发明授权

US06590797B1 Multi-bit programmable memory cell having multiple anti-fuse elements 有权
标题翻译：具有多个反熔丝元件的多位可编程存储单元
公开(公告)号：US06590797B1
公开(公告)日：2003-07-08
申请号：US10043677
申请日：2002-01-09
申请人： Ishai Nachumovsky , Yaov Nissan-Cohen , Robert J. Strain
发明人： Ishai Nachumovsky , Yaov Nissan-Cohen , Robert J. Strain
IPC分类号： G11C1700
CPC分类号： H01L27/112 , G11C11/5692 , G11C17/16
摘要： A multi-bit programmable memory cell is provided that includes an access transistor and a plurality of N anti-fuse elements. The access transistor has a source coupled to a source line and a gate coupled to a word line. Each of the anti-fuse elements has a first terminal coupled to a drain of the access transistor, and a second terminal coupled to a corresponding bit line. At most, only one of the anti-fuse elements is programmed. The memory cell is capable of storing M bits, wherein N=2M−1. A method is provided for both programming and reading the memory cell. In another embodiment, the anti-fuse elements can be replaced with mask-programmable elements.
摘要翻译：提供了一种多位可编程存储单元，其包括存取晶体管和多个N个反熔丝元件。存取晶体管具有耦合到源极线的源极和耦合到字线的栅极。每个反熔丝元件具有耦合到存取晶体管的漏极的第一端子和耦合到相应位线的第二端子。最多只有一个反熔丝元件被编程。存储单元能够存储M位，其中N = 2M-1。提供了编程和读取存储器单元的方法。在另一个实施例中，反熔丝元件可以用掩模可编程元件代替。

2. 发明授权

US6157570A Program/erase endurance of EEPROM memory cells 有权
标题翻译： EEPROM存储单元的编程/擦除耐久性
公开(公告)号：US6157570A
公开(公告)日：2000-12-05
申请号：US243973
申请日：1999-02-04
申请人： Ishai Nachumovsky
发明人： Ishai Nachumovsky
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34 , H01L27/115
CPC分类号： G11C16/3495 , G11C11/5671 , G11C16/0475 , G11C16/349 , H01L27/115
摘要： A circuit and method increases the endurance of memory cells in a memory array by decreasing the number of times a memory cell is programmed or erased. A bit-wise program/erase controller coupled to the memory array modifies the erasing and programming of multi-bit data words by erasing only those memory cells which must be erased and programming only those memory cells which must be programmed. Specifically, the bit-wise program/erase controller compares a new data word, which will be written into the memory array at a write address, with the current data word at the write address. The memory cells at the write address are categorized into a first subset and a second subset. The first subset of memory cells are currently in a programmed state but must be erased because the corresponding bit of the new data word is at an erased logic level. The second subset of memory cells are currently in an erased state but must be programmed because the corresponding bit of the new data word is at a programmed logic level. Bit-wise program/erase controller erases only the first subset of memory cells and programs only the second subset of memory cells. Thus, over multiple writes into the memory array, the number times each memory cell is erased or programmed is reduced resulting in greater endurance of the memory cells.
摘要翻译：电路和方法通过减少存储器单元被编程或擦除的次数来增加存储器阵列中存储单元的耐久性。耦合到存储器阵列的逐位程序/擦除控制器通过仅擦除必须擦除的那些存储器单元并且仅编程那些必须被编程的存储器单元来修改多位数据字的擦除和编程。具体来说，逐位编程/擦除控制器将在写入地址处将写入存储器阵列的新数据字与写入地址处的当前数据字进行比较。写地址处的存储单元被分类为第一子集和第二子集。存储器单元的第一子集当前处于编程状态，但必须被擦除，因为新数据字的相应位处于擦除的逻辑电平。存储器单元的第二子集当前处于擦除状态，但必须被编程，因为新数据字的相应位处于编程逻辑电平。逐位程序/擦除控制器仅擦除存储器单元的第一个子集，仅擦除存储器单元的第二个子集。因此，在对存储器阵列的多次写入中，每个存储单元被擦除或编程的次数减少，导致存储器单元的更大的耐久性。

3. 发明授权

US06181597B2 EEPROM array using 2-bit non-volatile memory cells with serial read operations 有权
标题翻译： EEPROM阵列使用具有串行读操作的2位非易失性存储单元
公开(公告)号：US06181597B2
公开(公告)日：2001-01-30
申请号：US09244317
申请日：1999-02-04
申请人： Ishai Nachumovsky
发明人： Ishai Nachumovsky
IPC分类号： G11C1604
CPC分类号： G11C16/26 , G11C11/5671 , G11C16/0475 , G11C16/0491 , H01L27/115
摘要： A structure and method for implementing an EEPROM array using 2-bit non-volatile memory cells arranged in a plurality of rows and columns. Each memory cell has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. A plurality of bit lines are provided, wherein each bit line is coupled to the first charge trapping region of each memory cell in one column and to the second charge trapping region of each memory cell in an adjacent column. A memory control circuit is coupled to the bit lines, wherein the memory control circuit erases a word stored in the EEPROM array by applying an erase voltage to one or more of the bit lines. The applied erase voltage erasing all of the charge trapping regions coupled to the one or more bit lines. All of the charge trapping regions erased in response to the erase voltage represent a single word of the EEPROM array. The memory control circuit reads a word stored in the EEPROM array by sequentially accessing all of the charge trapping regions coupled to one or more of the bit lines. Similarly, the memory control circuit writes a word to the EEPROM array by sequentially programming all of the charge trapping regions coupled to one or more of the bit lines.
摘要翻译：一种使用以多行和列排列的2位非易失性存储单元来实现EEPROM阵列的结构和方法。每个存储单元具有用于存储第一位的第一电荷捕获区和用于存储第二位的第二电荷捕获区。提供多个位线，其中每个位线耦合到一列中的每个存储单元的第一电荷俘获区域和相邻列中的每个存储单元的第二电荷俘获区域。存储器控制电路耦合到位线，其中存储器控制电路通过向一个或多个位线施加擦除电压来擦除存储在EEPROM阵列中的字。施加的擦除电压擦除耦合到一个或多个位线的所有电荷俘获区域。响应于擦除电压擦除的所有电荷捕获区域表示EEPROM阵列的单个字。存储器控制电路通过顺序访问耦合到一个或多个位线的所有电荷俘获区域来读取存储在EEPROM阵列中的字。类似地，存储器控制电路通过顺序编程耦合到一个或多个位线的所有电荷俘获区域将字写入EEPROM阵列。

4. 发明授权

US06174758B1 Semiconductor chip having fieldless array with salicide gates and methods for making same 有权
标题翻译：具有无闸门阵列的半导体芯片和其制造方法
公开(公告)号：US06174758B1
公开(公告)日：2001-01-16
申请号：US09261706
申请日：1999-03-03
申请人： Ishai Nachumovsky
发明人： Ishai Nachumovsky
IPC分类号： H01L218238
CPC分类号： H01L21/76221 , H01L21/76213 , H01L21/823412 , H01L21/823443
摘要： A semiconductor process, which creates a semiconductor devices that includes logic transistors fabricated in a first region and a fieldless array fabricated in a second region, is provided. Both the logic transistors and the fieldless array transistors have gates comprising a polysilicon layer with a silicide layer. The logic transistors have self-aligned silicide regions formed on their source and drain regions. Self-aligned silicide regions are not formed on the source and drain regions of the fieldless array transistors, thereby preventing undesirable electrical shorts which could otherwise occur within the fieldless array. The silicide structures can be fabricated by depositing polysilicon over the first and second regions, etching the polysilicon layer in the first region to define gates of the logic transistors, depositing and reacting a refractory metal, removing the non-reacted refractory metal, and then patterning the polysilicon and silicide in the second region to define gates of the fieldless array transistors.
摘要翻译：提供一种半导体工艺，其产生包括在第一区域中制造的逻辑晶体管和在第二区域中制造的无场阵列的半导体器件。逻辑晶体管和无场阵列晶体管都具有包括具有硅化物层的多晶硅层的栅极。逻辑晶体管具有在它们的源极和漏极区域上形成的自对准硅化物区域。自对准硅化物区域不形成在无场阵列晶体管的源极和漏极区域上，从而防止了在无场阵列中可能出现的不期望的电短路。可以通过在第一和第二区域上沉积多晶硅来制造硅化物结构，蚀刻第一区域中的多晶硅层以限定逻辑晶体管的栅极，沉积和反应难熔金属，去除未反应的难熔金属，然后图案化第二区域中的多晶硅和硅化物以限定无栅阵列晶体管的栅极。

5. 发明授权

US06809948B2 Mask programmable read-only memory (ROM) cell 失效
标题翻译：掩模可编程只读存储器（ROM）单元
公开(公告)号：US06809948B2
公开(公告)日：2004-10-26
申请号：US10430931
申请日：2003-05-06
申请人： Ishai Nachumovsky , Yaov Nissan-Cohen , Robert J. Strain
发明人： Ishai Nachumovsky , Yaov Nissan-Cohen , Robert J. Strain
IPC分类号： G11C1700
CPC分类号： H01L27/112 , G11C11/5692 , G11C17/16
摘要： A multi-bit programmable memory cell is provided that includes an access transistor and a plurality of N anti-fuse elements. The access transistor has a source coupled to a source line and a gate coupled to a word line. Each of the anti-fuse elements has a first terminal coupled to a drain of the access transistor, and a second terminal coupled to a corresponding bit line. At most, only one of the anti-fuse elements is programmed. The memory cell is capable of storing M bits, wherein N=2M−1. A method is provided for both programming and reading the memory cell. In another embodiment, the anti-fuse elements can be replaced with mask-programmable elements.
摘要翻译：提供了一种多位可编程存储单元，其包括存取晶体管和多个N个反熔丝元件。存取晶体管具有耦合到源极线的源极和耦合到字线的栅极。每个反熔丝元件具有耦合到存取晶体管的漏极的第一端子和耦合到相应位线的第二端子。最多只有一个反熔丝元件被编程。存储单元能够存储M位，其中N = 2-M -1。提供了编程和读取存储器单元的方法。在另一个实施例中，反熔丝元件可以用掩模可编程元件代替。

6. 发明授权

US06256231B1 EEPROM array using 2-bit non-volatile memory cells and method of implementing same 有权
标题翻译：使用2位非易失性存储单元的EEPROM阵列及其实现方法
公开(公告)号：US06256231B1
公开(公告)日：2001-07-03
申请号：US09244529
申请日：1999-02-04
申请人： Yoav Lavi , Ishai Nachumovsky
发明人： Yoav Lavi , Ishai Nachumovsky
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C16/24 , H01L27/11519 , H01L27/11521 , H01L29/7887
摘要： A structure and method for implementing an EEPROM using 2-bit non-volatile memory cells. Each memory cell has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. The memory cells are arranged in one or more rows, with a word line coupling the gates of all of the memory cells in each row. Diffusion bit lines couple the first charge trapping region of each memory cell with the second charge trapping region of an adjacent memory cell. When the first charge trapping region of a memory cell is erased, the second charge trapping region of the adjacent memory cell is incidentally erased. This incidental erasure is effectively avoided by: (1) reading the bit stored in the second charge trapping region, (2) writing this bit to a storage device, (3) performing the erase operation, and then (4) restoring the bit from the storage device to the second charge trapping region of the adjacent memory cell. If an erase operation results in the incidental erasure of additional bits (as will occur when more than one row of memory cells is coupled to a single diffusion bit line), then all of the bits that would be incidentally erased are written to the storage device before the erase operation, and are restored to the array after the erase operation. The incidental erasure can also be rendered moot by using only one charge trapping region of each memory cell.
摘要翻译：一种使用2位非易失性存储单元实现EEPROM的结构和方法。每个存储单元具有用于存储第一位的第一电荷捕获区和用于存储第二位的第二电荷捕获区。存储单元布置成一行或多行，字线将每行中的所有存储单元的栅极耦合。扩散位线将每个存储单元的第一电荷俘获区域与相邻存储单元的第二电荷俘获区域耦合。当擦除存储单元的第一电荷俘获区域时，相邻的存储单元的第二电荷俘获区被附带地擦除。通过以下方式有效地避免了这种偶然的擦除：（1）读取存储在第二电荷俘获区域中的位，（2）将该位写入存储装置，（3）执行擦除操作，然后（4）存储设备到相邻存储器单元的第二电荷俘获区域。如果擦除操作导致附加位的偶然擦除（当多于一行存储器单元耦合到单个扩散位线时将发生），则将被附带地擦除的所有位被写入存储设备在擦除操作之前，并且在擦除操作之后恢复到阵列。也可以通过仅使用每个存储单元的一个电荷捕获区域来实现偶然擦除。

7. 发明授权

US06871307B2 Efficient test structure for non-volatile memory and other semiconductor integrated circuits 有权
标题翻译：非易失性存储器和其他半导体集成电路的高效测试结构
公开(公告)号：US06871307B2
公开(公告)日：2005-03-22
申请号：US09975064
申请日：2001-10-10
申请人： Ishai Nachumovsky
发明人： Ishai Nachumovsky
IPC分类号： G11C29/00 , G11C29/48 , G01R27/08
CPC分类号： G11C29/006 , G11C29/48
摘要： A test system includes a test wafer having non-volatile memory dies and an exposed set of pads. A probe wafer includes test circuitry, a first set of pads exposed at a first surface, a second set of pads exposed at a second surface (opposite the first surface), and an interconnect structure. The interconnect structure includes traces that extend through the probe card or around the edges of the probe card, between the first and second surfaces. A prober aligns the test wafer with the probe wafer, such that the pads of the test wafer contact the first set of pads of the probe wafer. The prober further contacts the second set of pads of the probe wafer, and provides connections between these pads and a tester. The probe wafer is fabricated using semiconductor processing techniques, so that precise alignment exists between the test wafer and the probe wafer.
摘要翻译：测试系统包括具有非易失性存储器管芯和暴露的焊盘的测试晶片。探针晶片包括测试电路，在第一表面暴露的第一组焊盘，在第二表面（与第一表面相对）暴露的第二组焊盘，以及互连结构。互连结构包括在第一和第二表面之间延伸穿过探针卡或探针卡的边缘周围的迹线。探测器将测试晶片与探针晶片对准，使得测试晶片的焊盘接触探针晶片的第一组焊盘。探测器进一步接触探针晶片的第二组焊盘，并提供这些焊盘和测试仪之间的连接。使用半导体处理技术制造探针晶片，使得在测试晶片和探针晶片之间精确对准。

8. 发明授权

US06218695B1 Area efficient column select circuitry for 2-bit non-volatile memory cells 有权
标题翻译： 2位非易失性存储单元的区域高效列选择电路
公开(公告)号：US06218695B1
公开(公告)日：2001-04-17
申请号：US09340979
申请日：1999-06-28
申请人： Ishai Nachumovsky
发明人： Ishai Nachumovsky
IPC分类号： H01L27108
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0475 , H01L27/115
摘要： A memory circuit that includes a series of parallel elongated diffusion bit lines and an array of 2-bit non-volatile memory cells connected between the diffusion bit lines. Column select circuits are located at the ends of the diffusion bits lines that selectively connect the diffusion bit lines to a bit line decoder circuit to read appropriate signals from selected memory cells. A series of metal jumpers extend over and connect the ends of the diffusion bit lines. By connecting both ends of the diffusion bit lines together, the metal jumpers allow the diffusion bit lines to be longer without increasing resistance, so that a single pair of column select circuit control a large number of memory cells to increase the area efficiency of the memory array. Conversely, the metal jumpers reduce the resistance in shorter diffusion bit lines, thereby increasing memory array endurance.
摘要翻译：一种包括一系列平行细长扩散位线和连接在扩散位线之间的2位非易失性存储单元的阵列的存储器电路。列选择电路位于扩散位线的端部，其选择性地将扩散位线连接到位线解码器电路以从选择的存储器单元读取适当的信号。一系列金属跳线延伸并连接扩散位线的两端。通过将扩散位线的两端连接在一起，金属跳线允许扩散位线更长而不增加电阻，使得单对列选择电路控制大量存储器单元以增加存储器的面积效率数组。相反，金属跳线减少了较短扩散位线中的电阻，从而增加了存储器阵列的耐久性。

9. 发明授权

US6044022A Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays 有权
标题翻译：包括2位非易失性存储单元阵列的EEPROMS的可编程配置
公开(公告)号：US6044022A
公开(公告)日：2000-03-28
申请号：US258059
申请日：1999-02-26
申请人： Ishai Nachumovsky
发明人： Ishai Nachumovsky
IPC分类号： G11C11/56 , G11C16/04 , G11C16/26
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/26 , G11C19/00 , G11C2211/5641 , G11C8/04
摘要： A structure and method for configuring an EEPROM having an array of 2-bit non-volatile memory transistors to perform either in a high-speed 1-bit operation mode or a high-density 2-bit operation mode. Each memory transistor has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. The selected operation mode is determined by configuration data set by the EEPROM manufacturer in accordance with a customer's requirements. In one embodiment, an EEPROM includes blocks of memory cells accessed by a single word line. When the configuration data indicates the 1-bit operation mode, the memory control circuit stores data in only one of the two charge trapping regions of each memory cell. All eight bits of a word are read simultaneously by accessing eight separate charge trapping regions. Conversely, when the configuration data indicates the 2-bit operation mode, the memory control circuit stores data in both charge trapping regions of each memory cell. A read operation in the 2-bit operation mode requires reading a first group of four bits during a first stage, and then reading a second group of four bits during a second stage. These first and second groups of bits are successively stored in a shift register, and then transmitted to an I/O control circuit.
摘要翻译：一种用于配置具有2位非易失性存储晶体管阵列的EEPROM以在高速1位操作模式或高密度2位操作模式中执行的结构和方法。每个存储晶体管具有用于存储第一位的第一电荷俘获区和用于存储第二位的第二电荷捕获区。所选择的操作模式由EEPROM制造商根据客户要求设置的配置数据确定。在一个实施例中，EEPROM包括由单个字线访问的存储器单元的块。当配置数据指示1位操作模式时，存储器控制电路仅将数据存储在每个存储器单元的两个电荷捕获区域中的一个中。通过访问八个单独的电荷捕获区域，一个字的所有8位同时读取。相反，当配置数据指示2位操作模式时，存储器控制电路将数据存储在每个存储单元的两个电荷捕获区域中。在2位操作模式下的读取操作需要在第一级期间读取第一组四位，然后在第二级期间读取第二组四位。这些第一和第二组比特连续存储在移位寄存器中，然后发送到I / O控制电路。

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