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71. 发明申请

US20140332928A1 Digital Semiconductor Variable Capacitor 有权
标题翻译：数字半导体可变电容器
公开(公告)号：US20140332928A1
公开(公告)日：2014-11-13
申请号：US13889317
申请日：2013-05-07
申请人： Fabio Alessio Marino , Paolo Menegoli
发明人： Fabio Alessio Marino , Paolo Menegoli
IPC分类号： H01L29/93 , H01L29/66
CPC分类号： H01L29/93 , H01L29/66174 , H01L29/66189 , H01L29/94
摘要： A novel semiconductor variable capacitor is presented. The semiconductor structure is simple and is based on a semiconductor variable capacitor with MOS compatible structure suitable for integrated circuits, which has at least three terminals, one of which is used to modulate the capacitance value between the other two terminals of the device, by increasing or decreasing its DC voltage with respect to one of the main terminals of the device. Furthermore, the present invention decouples the AC signal and the DC control voltage preventing distortion of the RF signal. The present invention describes a controllable capacitor whose capacitance value is not necessarily linear with its control voltage, but although possibly abrupt in its characteristic, is utilized to manufacture a semiconductor variable capacitor with digital control to improve its noise and linearity performance while maintaining high quality factor.
摘要翻译：介绍一种新型的半导体可变电容器。半导体结构简单，并且基于具有MOS兼容结构的半导体可变电容器，其适用于集成电路，其具有至少三个端子，其中一个用于通过增加器件的另外两个端子来调制电容值或者相对于设备的主端子之一降低其直流电压。此外，本发明解耦AC信号和DC控制电压，防止RF信号的失真。本发明描述了一种可控制的电容器，其电容值不一定与其控制电压成线性关系，但是尽管其特性可能突然地被用于制造具有数字控制的半导体可变电容器，以改善其噪声和线性性能，同时保持高品质因数。

72. 发明申请

US20140049315A1 Inversion Mode Varactor 有权
标题翻译：反转模式Varactor
公开(公告)号：US20140049315A1
公开(公告)日：2014-02-20
申请号：US14060835
申请日：2013-10-23
申请人： International Business Machines Corporation
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L27/1203 , H01L29/66174
摘要： In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：提供具有衬底，覆盖衬底的背栅层，覆盖在背栅层上的绝缘层，覆盖绝缘层的半导体层和至少一种金属氧化物半导体场效应晶体管（MOSFET）器件，其设置在所述半导体层上，其中所述半导体层包括源极区和漏极区，其中所述至少一个MOSFET器件包括限定所述源极区和所述漏极区之间的沟道的栅极叠层，其中所述栅极堆叠具有覆盖所述半导体层的栅极介电层和覆盖所述栅极介电层的导电层; 以及向所述背栅层施加偏置电压，以在所述半导体层和所述绝缘层之间的界面处在所述半导体层中形成反转区域。

73. 发明授权

US08633565B2 Semiconductor device including fuse having form of capacitor 有权
标题翻译：包括具有电容器形式的熔丝的半导体装置
公开(公告)号：US08633565B2
公开(公告)日：2014-01-21
申请号：US12840375
申请日：2010-07-21
申请人： Ho-Ju Song , Seong-Ho Kim , Won-Mo Park , Gil-Sub Kim
发明人： Ho-Ju Song , Seong-Ho Kim , Won-Mo Park , Gil-Sub Kim
IPC分类号： H01L29/93
CPC分类号： H01L23/5256 , H01L27/105 , H01L27/10852 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode.
摘要翻译：半导体器件包括具有电容器形式的熔丝。半导体器件包括形成在半导体衬底上的阴极，阴极上形成的阳极，以及形成在阴极和阳极之间并且电连接阴极和阳极的至少一个具有圆柱壳形状的灯丝。

74. 发明授权

US08471359B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08471359B2
公开(公告)日：2013-06-25
申请号：US12656746
申请日：2010-02-16
申请人： Weon-Hong Kim , Min-Woo Song , Jung-Min Park
发明人： Weon-Hong Kim , Min-Woo Song , Jung-Min Park
IPC分类号： H01L29/93
CPC分类号： H01L28/60 , H01L21/02178 , H01L21/02189 , H01L21/022 , H01L21/02274 , H01L21/0228 , H01L21/3142 , H01L21/31604 , H01L21/31641 , H01L27/10852 , H01L28/40
摘要： A semiconductor device including a substrate; a bottom electrode on the substrate; a first dielectric layer on the bottom electrode, the first dielectric layer including a first metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb; a second dielectric layer on the first dielectric layer, the second dielectric layer including a second metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb, wherein the first metal oxide and the second metal oxide are different materials; a third dielectric layer on the second dielectric layer, the third dielectric layer including a metal carbon oxynitride; and an upper electrode on the third dielectric layer.
摘要翻译：一种包括衬底的半导体器件; 基底上的底电极; 所述第一电介质层包括包含Hf，Al，Zr，La，Ba，Sr，Ti和Pb中的至少一种的第一金属氧化物; 在所述第一电介质层上的第二电介质层，所述第二电介质层包括包含Hf，Al，Zr，La，Ba，Sr，Ti和Pb中的至少一种的第二金属氧化物，其中所述第一金属氧化物和所述第二金属氧化物是不同的材料; 第二电介质层上的第三电介质层，第三电介质层包括金属碳氮氧化物; 以及第三电介质层上的上电极。

75. 发明授权

US08450832B2 Large tuning range junction varactor 有权
标题翻译：大调谐范围结变容二极管
公开(公告)号：US08450832B2
公开(公告)日：2013-05-28
申请号：US11696732
申请日：2007-04-05
申请人： Manju Sarkar , Purakh Raj Verma
发明人： Manju Sarkar , Purakh Raj Verma
IPC分类号： H01L29/93
CPC分类号： H01L27/0808 , H01L29/93
摘要： Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.
摘要翻译：大型调谐范围结变容二极管包括并联在第一和第二变容二极管端子之间的第一和第二结电容器。电容器的第一和第二板由衬底中的三个交替掺杂区域形成。第一和第三掺杂区域具有夹着第二类型的第二掺杂区域的相同类型。第一输入端子耦合到第一和第三掺杂区域，第二端子耦合到第二掺杂区域。在掺杂区域的界面处是第一和第二耗尽区域，其宽度可以通过将端子间的电压从零改变为全反向偏压来改变。

76. 发明申请

US20120235731A1 CONTINUOUS TUNABLE LC RESONATOR USING A FET AS A VARACTOR 有权
标题翻译：使用FET作为变送器的连续可调谐LC谐振器
公开(公告)号：US20120235731A1
公开(公告)日：2012-09-20
申请号：US13427488
申请日：2012-03-22
申请人： Bin Li , Peter J. Zampardi, JR. , Andre G. Metzger
发明人： Bin Li , Peter J. Zampardi, JR. , Andre G. Metzger
IPC分类号： G05F3/02 , H01L21/8248 , H01Q23/00 , H01L29/93
CPC分类号： H01L27/0635 , H01L21/8249 , H01L27/0605 , H01L27/0623 , H01L27/0808 , H01L27/0811 , H01L29/1095 , H01L29/93 , H01L29/94 , H03J3/185
摘要： A varactor includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage applied to the back gate of the FET creates a continuously variable capacitance in a channel of the FET.
摘要翻译：变容二极管包括与双极结型晶体管（BJT）的至少一部分集成的场效应晶体管（FET），其中FET的背栅与BJT的基极共享电连接，并且其中反向电压施加到FET的背栅极在FET的沟道中产生连续可变的电容。

77. 发明授权

US08115281B2 Differential varactor 有权
标题翻译：差分变容二极管
公开(公告)号：US08115281B2
公开(公告)日：2012-02-14
申请号：US12124073
申请日：2008-05-20
申请人： Adam H. Pawlikiewicz , Samir el Rai
发明人： Adam H. Pawlikiewicz , Samir el Rai
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L29/66174 , H01L29/94
摘要： A high-Q differential varactor includes reduced inner spacing dimensions between differential fingers.
摘要翻译：高Q差分变容二极管包括微分手指之间的内部间距尺寸减小。

78. 发明授权

US08049307B2 Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices 有权
标题翻译：绝缘栅双极晶体管（IGBT）静电放电（ESD）保护器件
公开(公告)号：US08049307B2
公开(公告)日：2011-11-01
申请号：US12358943
申请日：2009-01-23
申请人： Yeh-Ning Jou , Shang-Hui Tu , Jui-Chun Chang , Chen-Wei Wu
发明人： Yeh-Ning Jou , Shang-Hui Tu , Jui-Chun Chang , Chen-Wei Wu
IPC分类号： H01L29/93
CPC分类号： H01L29/7393 , H01L27/0259
摘要： Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.
摘要翻译：介绍了绝缘栅双极晶体管（IGBT）静电放电（ESD）保护装置。 IGBT-ESD器件包括半导体衬底和设置在半导体衬底上的图案化绝缘区域，其限定第一有源区域和第二有源区域。在半导体衬底的第一有源区中形成高V N阱。在半导体衬底的第二有源区中形成P体掺杂区域，其中高V N阱和P体掺杂区域以暴露半导体衬底的预定距离被分离。 P +掺杂漏区设置在高V N阱中。 P +扩散区域和N +掺杂源极区域设置在P体掺杂区域中。栅极结构设置在半导体衬底上，其一端与N +掺杂源极区相邻，另一端延伸在绝缘区上。

79. 发明申请

US20110108952A1 MEMORY CAPACITOR MADE FROM FIELD CONFIGURABLE ION-DOPED MATERIALS 有权
标题翻译：来自现场可配置离子材料的记忆体电容
公开(公告)号：US20110108952A1
公开(公告)日：2011-05-12
申请号：US12941005
申请日：2010-11-05
申请人： Yong Chen
发明人： Yong Chen
IPC分类号： H01L29/93
CPC分类号： H01L28/40 , H01L27/1085 , H01L27/285
摘要： A memory capacitor based on a field configurable ion-doped polymer is reported. The device can be dynamically and reversibly programmed to analog capacitances with low-voltage (
摘要翻译：报道了一种基于现场可配置离子掺杂聚合物的存储电容器。该器件可以动态可逆地编程为具有低电压（<5 V）脉冲的模拟电容。器件编程为特定值后，其电容保持不变。场可配置电容归因于聚合物中离子掺杂剂浓度的改变。当施加到电极的电压偏压超过阈值时，可以修改离子导电层中的离子和偶极子浓度，并且当施加小于阈值的电压时可以作为常规电容器工作。器件修改后，离子导电层将保持在稳定的值，而不施加外部电压。即使外部电压关闭，该器件也具有非易失性存储功能。存储电容器可用于模拟存储器，非线性模拟和神经元电路。

80. 发明授权

US07868416B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07868416B2
公开(公告)日：2011-01-11
申请号：US12773038
申请日：2010-05-04
申请人： Hiroyasu Tanaka , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Yoshiaki Fukuzumi , Masaru Kito , Yasuyuki Matsuoka
发明人： Hiroyasu Tanaka , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Yoshiaki Fukuzumi , Masaru Kito , Yasuyuki Matsuoka
IPC分类号： H01L29/93 , H01L21/76
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L29/0649 , H01L29/7923 , H01L29/7926
摘要： A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.
摘要翻译：半导体器件具有衬底，形成在衬底的表面部分上的源极区域，形成在衬底上的第一绝缘层，形成在第一绝缘层上的栅电极，形成在栅电极上的第二绝缘层，主体与源极区域连接，穿过第一绝缘层，栅电极和第二绝缘层，并且包含空隙，围绕主体部分的栅极绝缘膜，并且形成在主体部分和栅电极之间，并且漏极区域与主体部分连接。

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