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71. 发明授权

US07394068B2 Mask inspection apparatus, mask inspection method, and electron beam exposure system 有权
标题翻译：掩模检查装置，掩模检查方法和电子束曝光系统
公开(公告)号：US07394068B2
公开(公告)日：2008-07-01
申请号：US11235727
申请日：2005-09-26
申请人： Hiroshi Yasuda , Takeshi Haraguchi
发明人： Hiroshi Yasuda , Takeshi Haraguchi
IPC分类号： H01L21/66
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/84 , H01J37/3174 , H01J2237/2817
摘要： A mask inspection apparatus includes: an electron gun for generating an electron beam; an exposure mask for shaping the electron beam into a predetermined cross-sectional shape; means for scanning the electron beam shaped by the exposure mask; means for selecting and transmitting part of the shaped electron beam, which selecting means includes a thin film having a small transmission aperture transmitting the electron beam scanned by the scanning means and includes a thick substrate having an opening larger than the small transmission aperture and a thickness greater than that of the thin film; and means for detecting the electron beam passed through the selecting means and outputting a current signal. The detecting means includes: a reflective body for reflecting the electron beam selected by the selecting means; and a detector for detecting the electron beam reflected by the reflective body.
摘要翻译：掩模检查装置包括：用于产生电子束的电子枪; 用于将电子束成形为预定横截面形状的曝光掩模; 用于扫描由曝光掩模形成的电子束的装置; 用于选择和传送部分成形电子束的装置，该选择装置包括具有传输由扫描装置扫描的电子束的小透射孔的薄膜，并且包括具有大于小透射孔的开口的厚基底和厚度大于薄膜; 以及用于检测通过选择装置的电子束并输出电流信号的装置。检测装置包括：用于反射由选择装置选择的电子束的反射体; 以及用于检测由反射体反射的电子束的检测器。

72. 发明授权

US07276920B2 Packaging and interconnection of contact structure 失效
标题翻译：接触结构的包装和互连
公开(公告)号：US07276920B2
公开(公告)日：2007-10-02
申请号：US09929532
申请日：2001-08-13
申请人： Mark R. Jones , Theodore A. Khoury
发明人： Mark R. Jones , Theodore A. Khoury
IPC分类号： G01R31/02
CPC分类号： G01R1/06744 , G01R3/00 , H01R4/04 , H01R13/2414
摘要： A packaging and interconnection for connecting a contact structure to an outer peripheral component. The packaging and interconnection includes a contact structure made of conductive material and formed on a contact substrate, a contact trace formed on the contact substrate and connected to the contact structure, a contact pad formed on a bottom surface of the contact substrate and connected to the contact structure through a via hole and the contact trace, a contact target provided at an outer periphery of the contact structure to be electrically connected with the contact pad, and a conductive member for connecting the contact pad and the contact target.
摘要翻译：用于将接触结构连接到外周部件的包装和互连。包装和互连包括由导电材料制成并形成在接触基板上的接触结构，形成在接触基板上并连接到接触结构的接触迹线，形成在接触基板的底表面上并连接到接触基板上的接触焊盘接触结构通过通孔和接触迹线，设置在接触结构的外周边以与接触焊盘电连接的接触目标，以及用于连接接触焊盘和接触靶的导电部件。

73. 发明授权

US07240269B2 Timing generator and semiconductor testing device 失效
标题翻译：定时发生器和半导体测试装置
公开(公告)号：US07240269B2
公开(公告)日：2007-07-03
申请号：US11126038
申请日：2005-05-10
申请人： Takashi Ochi
发明人： Takashi Ochi
IPC分类号： G01R31/28 , G06F11/00 , G06F1/12
CPC分类号： G01R31/31709 , G01R31/31922
摘要： A timing generator f or a semiconductor test device reduces pattern-dependent jitters and timing errors of timing pulse signals. In the timing generator, a delaying circuit (variable delaying means, clock signal delaying circuit) is disposed on an input terminal side of a clock signal of a signal input/output circuit having the flip-flop (reference signal delaying means) which outputs an output signal in accordance with an input timing of the delayed clock signal. The clock signal is delayed by the delaying circuit. The clock signal delaying circuit may be replaced with a phase locked loop circuit.
摘要翻译：定时发生器f或半导体测试装置减少定时脉冲信号的图形相关抖动和定时误差。在定时发生器中，延迟电路（可变延迟装置，时钟信号延迟电路）设置在具有触发器（参考信号延迟装置）的信号输入/输出电路的时钟信号的输入端侧，输出端根据延迟的时钟信号的输入定时输出信号。时钟信号被延迟电路延迟。时钟信号延迟电路可以用锁相环电路代替。

74. 发明授权

US07089517B2 Method for design validation of complex IC 失效
标题翻译：复杂IC设计验证方法
公开(公告)号：US07089517B2
公开(公告)日：2006-08-08
申请号：US09941396
申请日：2001-08-28
申请人： Hiroaki Yamoto , Rochit Rajsuman
发明人： Hiroaki Yamoto , Rochit Rajsuman
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G06F11/261 , G06F17/5022
摘要： A method for design validation of complex IC with use of a combination of electronic design automation (EDA) tools and a design test station at high speed and low cost. The EDA tools and device simulator are linked to the event based test system to execute the original design simulation vectors and testbench and make modifications in the testbench and event based test vectors until satisfactory results are obtained. The event based test vectors are test vectors in an event format in which an event is any change in a signal which is described by its timing and the event based test system is a test system for testing an IC by utilizing the event based test vectors. Because EDA tools are linked with the event based test system, these modifications are captured to generate a final testbench that provides satisfactory results.
摘要翻译：利用电子设计自动化（EDA）工具和设计测试站的组合，以高速，低成本的方式对复杂IC进行设计验证。 EDA工具和设备模拟器链接到基于事件的测试系统，以执行原始设计模拟向量和测试平台，并在测试平台和基于事件的测试向量中进行修改，直到获得满意的结果。基于事件的测试向量是事件格式中的测试向量，其中事件是由其定时描述的信号中的任何变化，并且基于事件的测试系统是通过利用基于事件的测试向量来测试IC的测试系统。由于EDA工具与基于事件的测试系统相关联，因此捕获这些修改以生成最终的测试平台，从而提供令人满意的结果。

75. 发明授权

US07078889B2 Semiconductor test apparatus for testing semiconductor device that produces output data by its internal clock timing 失效
标题翻译：用于测试通过其内部时钟时序产生输出数据的半导体器件的半导体测试装置
公开(公告)号：US07078889B2
公开(公告)日：2006-07-18
申请号：US10507042
申请日：2003-12-26
申请人： Hideyuki Oshima
发明人： Hideyuki Oshima
IPC分类号： G01R31/26
CPC分类号： G01R31/31922
摘要： A recovery clock synchronized with an internal clock faster than a system clock is obtained with an edge timing of the system clock output from a DUT. The present invention includes: a time interpolator 20 which includes flip-flops (FF 21) which receive system clocks of the DUT 1, a delay circuit 22 which outputs time-series level data, from the FF 21, and an encoder 28 which receives the time-series level data output and encodes it into positional data indicative of an edge timing; a digital filter 40 which includes a plurality of registers 41 which sequentially store the positional data and output the positional data as a recovery clock; and a data side selector 30 which selects output data of the DUT 1 base on the recovery clock.
摘要翻译：在系统时钟从DUT的输出的边沿定时获得与系统时钟相比内部时钟同步的恢复时钟。本发明包括：时间插补器20，其包括接收DUT1的系统时钟的触发器（FF21），从FF21输出时间序列电平数据的延迟电路22和接收时间序列电平数据输出并将其编码成表示边缘定时的位置数据; 数字滤波器40，其包括多个寄存器41，其顺序地存储位置数据并输出位置数据作为恢复时钟; 以及数据侧选择器30，其基于恢复时钟选择DUT 1的输出数据。

76. 发明授权

US07041988B2 Electron beam exposure apparatus and electron beam processing apparatus 失效
标题翻译：电子束曝光装置和电子束处理装置
公开(公告)号：US07041988B2
公开(公告)日：2006-05-09
申请号：US10431782
申请日：2003-05-08
申请人： Shinichi Hamaguchi , Susumu Goto , Osamu Kamimura , Yasunari Sohda
发明人： Shinichi Hamaguchi , Susumu Goto , Osamu Kamimura , Yasunari Sohda
IPC分类号： G21G5/00 , G21K5/10
CPC分类号： B82Y10/00 , B82Y40/00 , G21K1/093 , H01J37/153 , H01J37/3177 , H01J2237/1536
摘要： An electron beam exposure apparatus for exposing wafer with an electron beam, includes: a first electromagnetic lens system for making the electron beam incident substantially perpendicularly on a first plane be incident on a second plane substantially perpendicularly; a second electromagnetic lens system for making the electron beam that was substantially perpendicularly incident on the second plane be incident on the wafer substantially perpendicularly; a rotation correction lens provided within the first electromagnetic lens system for correcting rotation of the electron beam caused by at least the first electromagnetic lens system; a deflection system for deflecting the electron beam to a position on the wafer; and a deflection-correction optical system provided within the second electromagnetic lens system for correcting deflection aberration caused by the deflection system.
摘要翻译：一种用电子束曝光晶片的电子束曝光装置，包括：用于使基本上垂直于第一平面的电子束入射到第二平面上的第一电磁透镜系统基本垂直入射; 用于使基本上垂直入射在第二平面上的电子束的第二电磁透镜系统基本上垂直入射在晶片上; 旋转校正透镜，设置在第一电磁透镜系统内，用于校正由至少第一电磁透镜系统引起的电子束的旋转; 用于将电子束偏转到晶片上的位置的偏转系统; 以及设置在第二电磁透镜系统内用于校正由偏转系统引起的偏转像差的偏转校正光学系统。

77. 发明授权

US07034518B2 Timing generator and semiconductor test apparatus 失效
标题翻译：定时发生器和半导体测试装置
公开(公告)号：US07034518B2
公开(公告)日：2006-04-25
申请号：US10484980
申请日：2002-07-26
申请人： Kazuhiro Yamamoto
发明人： Kazuhiro Yamamoto
IPC分类号： G01R31/26
CPC分类号： G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00071 , H03K2005/00084
摘要： There is provided a timing generator capable of absorbing a delay time error of a variable delay circuit without increasing the number of bits of path data and suppressing deterioration of the timing accuracy from the designed value to the minimum. The timing generator is configured to include a selection unit which assigns five-bit delay device candidates to a three-bit partial bit signal of all the bit signals constituting the path data outputted from a linearization memory and selects three delay devices whose number is equal to the bit count of the partial bit signal.
摘要翻译：提供一种能够吸收可变延迟电路的延迟时间误差的定时发生器，而不增加路径数据的位数，并将定时精度的降低从设计值降低到最小。定时发生器被配置为包括一个选择单元，该选择单元将构成从线性化存储器输出的路径数据的所有比特信号的3比特部分比特信号分配给5比特延迟装置候选，并且选择三个等于部分位信号的位计数。

78. 发明申请

US20020089343A1 Contact structure for electrical communication with contact targets 失效
标题翻译：与接触目标电气通信的接触结构
公开(公告)号：US20020089343A1
公开(公告)日：2002-07-11
申请号：US10058951
申请日：2002-01-28
申请人： Advantest Corp.
发明人： Theodore A. Khoury , Mark R. Jones , James W. Frame
IPC分类号： G01R031/02
CPC分类号： G01R3/00 , G01R1/06711 , G01R1/07342
摘要： A contact structure for testing a semiconductor wafer, a packaged LSI or a printed circuit board is formed on a planar surface of a substrate by a photolithography technology. The contact structure is formed of a silicon base having an inclined support portion created through an anisotropic etching process, an insulation layer formed on the silicon base and abutted from the inclined support, and a conductive layer made of conductive material formed on the insulation layer so that a beam portion is created by the insulation layer and the conductive layer, where wherein the beam portion exhibits a spring force in a transversal direction of the beam portion to establish a contact force when the tip of the beam portion pressed against a contact target.
摘要翻译：通过光刻技术在基板的平面上形成用于测试半导体晶片，封装LSI或印刷电路板的接触结构。接触结构由具有通过各向异性蚀刻工艺形成的倾斜支撑部分的硅基底，形成在硅基底上并与倾斜支撑件抵接的绝缘层和由形成在绝缘层上的导电材料制成的导电层形成梁部分由绝缘层和导电层产生，其中梁部分在梁部分的横向方向上呈现弹簧力，以在梁部分的尖端压靠接触目标时建立接触力。

79. 发明申请

US20020027444A1 Packaging and interconnection of contact structure 失效
标题翻译：接触结构的包装和互连
公开(公告)号：US20020027444A1
公开(公告)日：2002-03-07
申请号：US09929533
申请日：2001-08-13
申请人： Advantest Corp.
发明人： Mark R. Jones , Theodore A. Khoury
IPC分类号： G01R031/02
CPC分类号： G01R1/06744 , G01R3/00 , H01R4/04 , H01R13/2414
摘要： A packaging and interconnection of a contact structure formed of a contact structure made of conductive material and formed on a contact substrate through a micro-fabrication process, a contact pad connected to contact substrate and provided at the bottom surface of the contact substrate, a printed circuit board (PCB) pad provided on a printed circuit board (PCB) substrate to be electrically connected with the contact pad, a conductive member for connecting the contact pad the PCB pad, an elastomer provided under the contact substrate for allowing flexibility in the interconnection and packaging of the contact structure, and a support structure provided between the elastomer and the PCB substrate for supporting the contact structure, contact substrate and elastomer.
摘要翻译：由由导电材料制成的接触结构形成的接触结构和通过微加工工艺在接触基板上形成的接触结构的封装和互连，连接到接触基板并设置在接触基板的底表面处的接触焊盘，印刷设置在与接触焊盘电连接的印刷电路板（PCB）基板上的电路板（PCB）焊盘，用于将接触焊盘连接到PCB焊盘的导电部件，设置在接触基板下方的弹性体，用于允许互连中的灵活性和接触结构的包装，以及设置在弹性体和PCB基板之间的支撑结构，用于支撑接触结构，接触基底和弹性体。

80. 发明授权

US6081428A Cooling apparatus for electric devices 失效
标题翻译：电气设备冷却装置
公开(公告)号：US6081428A
公开(公告)日：2000-06-27
申请号：US41094
申请日：1998-03-12
申请人： Akihiro Fujimoto
发明人： Akihiro Fujimoto
IPC分类号： G01R31/28 , H01L23/433 , H05K7/20
CPC分类号： H01L23/433 , H01L2224/16 , H01L2224/73253 , H01L2924/01004
摘要： A cooling apparatus for cooling a plurality of electric devices mounted on a printed circuit board with high cooling efficiency and low cost. The cooling apparatus includes a cooling plate for receiving heat generated by said electric devices and transmitting the heat to an external area to cool the electric devices, an elastic sheet made of electrically insulating material and attached to the cooling plate for contacting surfaces of the electric devices, means for attaching the elastic sheet to the cooling plate in a manner to form a closed space therebetween, heat conductive springs provided in the closed space for pressing the elastic sheet toward the surfaces of the cooling plate, a heat distribution sheet provided between the elastic sheet and the heat conductive springs to distribute the heat received from the elastic sheet throughout the heat distribution sheet, and a layer of heat conductive grease applied between the heat distribution sheet and the heat conductive springs.
摘要翻译：一种用于以高冷却效率和低成本冷却安装在印刷电路板上的多个电气装置的冷却装置。冷却装置包括：冷却板，用于接收由所述电气装置产生的热量，并将热量传递到外部区域以冷却电气装置;由电绝缘材料制成的弹性片，并附接到冷却板，用于接触电气装置的表面用于将弹性片以形成封闭空间的方式安装在冷却板上的装置，设置在封闭空间内的热传导弹簧用于将弹性片朝向冷却板的表面挤压，设置在弹性片之间的配热片片材和导热弹簧以将从弹性片材接收的热量分布在整个配热片材中，以及一层导热油脂，其施加在配热片材和导热弹簧之间。

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