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71. 发明授权

US5583814A Semiconductor memory device, chain memory device, and data processing apparatus 失效
标题翻译：半导体存储器件，链式存储器件和数据处理设备
公开(公告)号：US5583814A
公开(公告)日：1996-12-10
申请号：US260361
申请日：1994-06-14
申请人： Masahiro Iwamura , Yutaka Kobayashi , Kei Kato
发明人： Masahiro Iwamura , Yutaka Kobayashi , Kei Kato
IPC分类号： G11C11/417 , G11C7/10 , G11C11/407 , G11C11/409 , G11C7/00
CPC分类号： G11C7/1051
摘要： An arrangement is provided for the input level of an output buffer from fluctuating when a memory device goes from an active state to an inactive state. To achieve this, a level holding circuit is provided at a point connecting an output of a sense circuit for amplifying a signal read from a memory array to an input of an output buffer. The level holding circuit is constituted so that, when the sense circuit goes from an active state to an inactive state, the level holding circuit holds an input level of the output buffer at a time immediately before the sense circuit goes inactive.
摘要翻译：当存储器件从活动状态变为非活动状态时，提供用于输出缓冲器的输入电平波动的布置。为了实现这一点，在连接用于放大从存储器阵列读取的信号的感测电路的输出到输出缓冲器的输入的点处提供电平保持电路。电平保持电路被构造成使得当感测电路从活动状态变为非活动状态时，电平保持电路在紧接在感测电路不活动之前的时间保持输出缓冲器的输入电平。

72. 发明授权

US5544125A Semiconductor integrated circuit having logic gates 失效
标题翻译：具有逻辑门的半导体集成电路
公开(公告)号：US5544125A
公开(公告)日：1996-08-06
申请号：US383866
申请日：1995-02-06
申请人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
发明人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
IPC分类号： G11C7/10 , G11C8/10 , H03K19/0948 , G11C8/00
CPC分类号： H03K19/0948 , G11C7/1051 , G11C7/1078 , G11C8/10
摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
摘要翻译：提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端信号，并且每个都耦合到公共节点。在一个实施例中，第一和第二开关元件也耦合到公共节点。第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。还提供了一种改进的读/写布置，用于这样的半导体存储器电路，其包括在写入操作期间防止公共读取线与数据线连接的电路。这通过在写入期间去除公共读取线的负载来增强写入速度。

73. 发明授权

US5542083A Information processor and information processing system utilizing clock signal 失效
标题翻译：信息处理器和利用时钟信号的信息处理系统
公开(公告)号：US5542083A
公开(公告)日：1996-07-30
申请号：US460601
申请日：1995-06-02
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/10 , H03K5/156 , H03L7/18 , G06F1/04
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controllled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
摘要翻译：一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时至少一对逻辑器件由时钟信号K1同步控制。

74. 发明授权

US5512847A BiCMOS tri-state output driver 失效
标题翻译： BiCMOS三态输出驱动器
公开(公告)号：US5512847A
公开(公告)日：1996-04-30
申请号：US321012
申请日：1994-10-06
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177 , H03K19/01
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

75. 发明授权

US5502820A Microprocessor having high speed, low noise output buffers 失效
标题翻译：微处理器具有高速，低噪声输出缓冲器
公开(公告)号：US5502820A
公开(公告)日：1996-03-26
申请号：US385656
申请日：1995-02-08
申请人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
发明人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/08 , H03K19/088 , H03K19/0944 , G06F13/00
CPC分类号： H03K19/09448 , H03K17/164 , H03K19/00361
摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
摘要翻译：提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

76. 发明授权

US5057713A Bipolar MOS logic circuit and semiconductor integrated circuit 失效
标题翻译：双极MOS逻辑电路和半导体集成电路
公开(公告)号：US5057713A
公开(公告)日：1991-10-15
申请号：US486419
申请日：1990-02-28
申请人： Masahiro Iwamura , Akira Ide
发明人： Masahiro Iwamura , Akira Ide
IPC分类号： H03K17/04 , H03K17/567 , H03K19/00 , H03K19/013 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/09448 , H03K19/001 , H03K19/0136
摘要： An invention is disclosed, which is suitable for operating a bipolar-MOS logic circuit, and in particular Bi-CMOS logic circuit with a low power supply voltage below 5V, e.g. around 3V. According to the present logic circuit, since the base current of a second NPN transistor is supplied from a power supply through a PMOS transistor (first current switching means), the impedance of which is lowered previously by a logic inverting means and an NMOS logic circuit (second current switching means), which is on/off controlled by an input signal, in a transient logic level transition period where the output is switched from the level "1" to "0" (i.e. it falls), it is possible to supply a sufficient base current to the second NPN. In this way, it is possible to turn-on the second NPN with a high speed and to pull down to the level "0" with high speed. Further, since the PMOS is switched off owing to the action of the logic inverting means just after having allowed a sufficient base current flow therethrough, the current path, through which the base current of the second NPN is supplied, is stopped and thus DC power consumption is elimated.
摘要翻译：公开了一种适用于操作双极MOS逻辑电路的发明，特别是具有低于5V的低电源电压的Bi-CMOS逻辑电路，例如， 3V左右根据本逻辑电路，由于第二NPN晶体管的基极电流通过PMOS晶体管（第一电流开关装置）从电源提供，其阻抗先前由逻辑反相装置和NMOS逻辑电路（第二电流切换装置），其在输出从电平“1”切换到“0”的瞬态逻辑电平转换周期（即，其下降）中，其由输入信号控制的开/关控制，向第二NPN提供足够的基极电流。以这种方式，可以高速打开第二个NPN并以高速下拉到“0”电平。此外，由于刚刚在允许足够的基极电流流动之后由于逻辑反相装置的作用使PMOS截止，所以提供第二NPN的基极电流的电流通路被停止，因此直流电力消费被淘汰。

77. 发明授权

US4907184A Arithmetic operation circuit 失效
标题翻译：算术运算电路
公开(公告)号：US4907184A
公开(公告)日：1990-03-06
申请号：US132368
申请日：1987-12-14
申请人： Tetsuo Nakano , Masahiro Iwamura , Kozaburo Kurita
发明人： Tetsuo Nakano , Masahiro Iwamura , Kozaburo Kurita
IPC分类号： H03K19/01 , G06F7/50 , G06F7/502 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/092
CPC分类号： G06F7/502
摘要： An arithmetic operation circuit is provided which includes a logic processing circuit having a first metal-oxide-semiconductor-field-effect-transistor (MOSFET) column cascade-connecting a plurality of MOSFETs and a second MOSFET column cascade-connecting a plurality of MOSFETs. First and second ends of the second MOSFET column are respectively connected to first and second ends of said first column. A first power supply voltage is coupled to the common connecting point of the first ends of said first and second MOSFET columns. An amplifying circuit, including the grounded emitter type bipolar transistor, is provided such that the base thereof is connected to the common connecting point of the second ends of said first and second MOSFET columns.
摘要翻译：提供了一种算术运算电路，其包括具有级联连接多个MOSFET的第一金属氧化物半导体场效应晶体管（MOSFET）列和串联连接多个MOSFET的第二MOSFET列的逻辑处理电路。第二MOSFET列的第一和第二端分别连接到所述第一列的第一和第二端。第一电源电压耦合到所述第一和第二MOSFET列的第一端的公共连接点。包括接地的发射极型双极晶体管的放大电路被设置成使得其基极连接到所述第一和第二MOSFET列的第二端的公共连接点。

78. 发明授权

US4853560A Logic circuit and semiconductor integrated circuit device capable of operating by different power supplies 失效
标题翻译：逻辑电路和半导体集成电路器件能够由不同的电源操作
公开(公告)号：US4853560A
公开(公告)日：1989-08-01
申请号：US149187
申请日：1988-01-27
申请人： Masahiro Iwamura , Hideo Maejima , Ikuro Masuda
发明人： Masahiro Iwamura , Hideo Maejima , Ikuro Masuda
IPC分类号： H03K19/0175 , H03K19/0185 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/017545 , H03K19/018585 , H03K19/09448
摘要： When a counter-part power supply designator of a first LSI designates that the counter-part power supply voltage of another LSI is a first power supply difference which is the same as the power supply difference of its own, an output circuit control controls an output circuit and the output circuit produces an output signal having a level adaptive to the counter-part LSI operating at the first power supply voltage. When the counter-part power supply voltage designator designates that the counter-part power supply voltage difference, lower than the first power supply voltage difference, the output circuit control controls the output circuit and the output circuit produces an output signal having a level adaptive to the counter-part LSI operating at the second power supply voltage difference. Thus, a plurality of LSIs can be operated at mutually different power supply voltages.
摘要翻译：当第一LSI的副部分电源指示符指定另一LSI的对方部分电源电压是与其自身的电源差相同的第一电源差时，输出电路控制控制输出电路和输出电路产生具有自适应于在第一电源电压下操作的对置部分LSI的电平的输出信号。当副部件电源电压指示符指定比第一电源电压差低的对置部分电源电压差时，输出电路控制器控制输出电路，并且输出电路产生具有自适应电平的电平的输出信号在第二电源电压差下工作的对置部分LSI。因此，可以在相互不同的电源电压下操作多个LSI。

79. 发明授权

US4808850A Composite circuit of bipolar transistors and field effect transistors 失效
标题翻译：双极晶体管和场效应晶体管的复合电路
公开(公告)号：US4808850A
公开(公告)日：1989-02-28
申请号：US129
申请日：1987-01-02
申请人： Ikuro Masuda , Masahiro Iwamura , Motohisa Nishihara
发明人： Ikuro Masuda , Masahiro Iwamura , Motohisa Nishihara
IPC分类号： H03K19/08 , H03K19/017 , H03K19/0944 , H03K19/02 , H03K17/60 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/017
摘要： A novel composite circuit comprises a first bipolar transistor with a collector of a first conductivity type connected to a first potential, an emitter of the first conductivity type connected to an output, a second bipolar transistor with a collector of the first conductivity type connected to the output and an emitter of the first conductivity type connected to a second potential, a field effect transistor of a second conductivity type with a gate connected to an input, a source connected to a third potential and a drain connected to the base of the first bipolar transistor, a field effect transistor of the first conductivity type with a gate connected to the input, a drain connected to the base of the first bipolar transistor, and a source connected to the base of the second bipolar transistor, and a unidirectional element inserted between the output and the drain of the field effect transistor of the first conductivity type and having a direction of rectification opposite to that of the PN junction formed between the base and emitter of the first bipolar transistor.

80. 发明授权

US4694202A Bi-MOS buffer circuit 失效
标题翻译： Bi-MOS缓冲电路
公开(公告)号：US4694202A
公开(公告)日：1987-09-15
申请号：US682197
申请日：1984-12-17
申请人： Masahiro Iwamura , Ikuro Masuda
发明人： Masahiro Iwamura , Ikuro Masuda
IPC分类号： H03K19/08 , H03K19/0175 , H03K19/094 , H03K19/0944 , H03K19/092 , H03K3/01 , H03K19/02 , H03K19/20
CPC分类号： H03K19/09448 , H03K19/09429
摘要： An improved buffer circuit is provided having an output stage for driving a load and a driver stage for driving said output stage. The output stage is constituted by a first MOS transistor to avoid problems found in bipolar output transistors which result from the amplitude of the output stage being influenced by the voltage V.sub.be of such output bipolar transistors. The driver stage, on the other hand, is formed of a bipolar transistor-MOS transistor composite logic cirucit. This driver stage includes an output circuit having a bipolar transistor for driving said first MOS transistor, and an input circuit including a second MOS transistor responsive to a predetermined input for rendering said bipolar transistor in the on or off state. The channel size of said first MOS transistor is larger than that of said second MOS transistor to give a device having an improved high operating speed.
摘要翻译：提供了一种改进的缓冲电路，具有用于驱动负载的输出级和用于驱动所述输出级的驱动级。输出级由第一MOS晶体管构成，以避免由输出级的振幅受到这种输出双极晶体管的电压Vbe的影响而产生的双极性输出晶体管中的问题。另一方面，驱动器级由双极晶体管MOS晶体管复合逻辑电路形成。该驱动器级包括具有用于驱动所述第一MOS晶体管的双极晶体管的输出电路和响应于预定输入的第二MOS晶体管的输入电路，用于使所述双极晶体管处于导通或截止状态。所述第一MOS晶体管的沟道尺寸大于所述第二MOS晶体管的沟道尺寸，以给出具有改善的高工作速度的器件。

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