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1. 发明授权

US5398318A High speed, low noise output buffer with non-identical pairs of output transistors 失效
标题翻译：具有不相同输出晶体管对的高速，低噪声输出缓冲器
公开(公告)号：US5398318A
公开(公告)日：1995-03-14
申请号：US608370
申请日：1990-11-02
申请人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
发明人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/08 , H03K19/088 , H03K19/0944 , G06F13/00
CPC分类号： H03K19/09448 , H03K17/164 , H03K19/00361
摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
摘要翻译：提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

2. 发明授权

US5675548A Semiconductor integrated circuit having logi gates 失效
标题翻译：具有逻辑门的半导体集成电路
公开(公告)号：US5675548A
公开(公告)日：1997-10-07
申请号：US608605
申请日：1996-02-29
申请人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
发明人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
IPC分类号： G11C7/10 , G11C8/10 , H03K19/0948 , G11C8/00
CPC分类号： H03K19/0948 , G11C7/1051 , G11C7/1078 , G11C8/10
摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
摘要翻译：提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端信号，并且每个都耦合到公共节点。在一个实施例中，第一和第二开关元件也耦合到公共节点。第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。还提供了一种用于这种半导体存储器电路的改进的读/写布置，该电路包括用于在写入操作期间公共读取线与数据线的连接的电路。这通过在写入期间去除公共读取线的负载来增强写入速度。

3. 发明授权

US5619151A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5619151A
公开(公告)日：1997-04-08
申请号：US473742
申请日：1995-06-07
申请人： Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yuji Yokoyama , Nozomu Matsuzaki , Tatsumi Yamauchi , Yutaka Kobayashi , Nobuyuki Gotou , Akira ide , Masahiro Yamamura , Hideaki Uchida
发明人： Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yuji Yokoyama , Nozomu Matsuzaki , Tatsumi Yamauchi , Yutaka Kobayashi , Nobuyuki Gotou , Akira ide , Masahiro Yamamura , Hideaki Uchida
IPC分类号： G11C7/10 , G11C8/06 , G11C8/10 , G11C8/18 , H03K5/1534 , H03K19/0175 , H03K5/153 , G01R29/02 , H03K3/033
CPC分类号： G11C7/1057 , G11C7/1051 , G11C8/06 , G11C8/10 , G11C8/18 , H03K19/017518 , H03K5/1534
摘要： A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.
摘要翻译：一种半导体存储器件，包括以下中的至少一个：（1）响应于输入地址产生内部地址信号的输入缓冲器电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据响应于ATD信号的时钟发生器的信号来控制器件的解码器，读出放大器和输出缓冲器。

4. 发明授权

US5544125A Semiconductor integrated circuit having logic gates 失效
标题翻译：具有逻辑门的半导体集成电路
公开(公告)号：US5544125A
公开(公告)日：1996-08-06
申请号：US383866
申请日：1995-02-06
申请人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
发明人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
IPC分类号： G11C7/10 , G11C8/10 , H03K19/0948 , G11C8/00
CPC分类号： H03K19/0948 , G11C7/1051 , G11C7/1078 , G11C8/10
摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
摘要翻译：提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端信号，并且每个都耦合到公共节点。在一个实施例中，第一和第二开关元件也耦合到公共节点。第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。还提供了一种改进的读/写布置，用于这样的半导体存储器电路，其包括在写入操作期间防止公共读取线与数据线连接的电路。这通过在写入期间去除公共读取线的负载来增强写入速度。

5. 发明授权

US5502820A Microprocessor having high speed, low noise output buffers 失效
标题翻译：微处理器具有高速，低噪声输出缓冲器
公开(公告)号：US5502820A
公开(公告)日：1996-03-26
申请号：US385656
申请日：1995-02-08
申请人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
发明人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/08 , H03K19/088 , H03K19/0944 , G06F13/00
CPC分类号： H03K19/09448 , H03K17/164 , H03K19/00361
摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
摘要翻译：提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

6. 发明授权

US5057713A Bipolar MOS logic circuit and semiconductor integrated circuit 失效
标题翻译：双极MOS逻辑电路和半导体集成电路
公开(公告)号：US5057713A
公开(公告)日：1991-10-15
申请号：US486419
申请日：1990-02-28
申请人： Masahiro Iwamura , Akira Ide
发明人： Masahiro Iwamura , Akira Ide
IPC分类号： H03K17/04 , H03K17/567 , H03K19/00 , H03K19/013 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/09448 , H03K19/001 , H03K19/0136
摘要： An invention is disclosed, which is suitable for operating a bipolar-MOS logic circuit, and in particular Bi-CMOS logic circuit with a low power supply voltage below 5V, e.g. around 3V. According to the present logic circuit, since the base current of a second NPN transistor is supplied from a power supply through a PMOS transistor (first current switching means), the impedance of which is lowered previously by a logic inverting means and an NMOS logic circuit (second current switching means), which is on/off controlled by an input signal, in a transient logic level transition period where the output is switched from the level "1" to "0" (i.e. it falls), it is possible to supply a sufficient base current to the second NPN. In this way, it is possible to turn-on the second NPN with a high speed and to pull down to the level "0" with high speed. Further, since the PMOS is switched off owing to the action of the logic inverting means just after having allowed a sufficient base current flow therethrough, the current path, through which the base current of the second NPN is supplied, is stopped and thus DC power consumption is elimated.
摘要翻译：公开了一种适用于操作双极MOS逻辑电路的发明，特别是具有低于5V的低电源电压的Bi-CMOS逻辑电路，例如， 3V左右根据本逻辑电路，由于第二NPN晶体管的基极电流通过PMOS晶体管（第一电流开关装置）从电源提供，其阻抗先前由逻辑反相装置和NMOS逻辑电路（第二电流切换装置），其在输出从电平“1”切换到“0”的瞬态逻辑电平转换周期（即，其下降）中，其由输入信号控制的开/关控制，向第二NPN提供足够的基极电流。以这种方式，可以高速打开第二个NPN并以高速下拉到“0”电平。此外，由于刚刚在允许足够的基极电流流动之后由于逻辑反相装置的作用使PMOS截止，所以提供第二NPN的基极电流的电流通路被停止，因此直流电力消费被淘汰。

7. 发明授权

US5680066A Signal transition detector circuit 失效
标题翻译：信号转换检测电路
公开(公告)号：US5680066A
公开(公告)日：1997-10-21
申请号：US182699
申请日：1994-01-13
申请人： Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yuji Yokoyama , Nozomu Matsuzaki , Tatsumi Yamauchi , Yutaka Kobayashi , Nobuyuki Gotou , Akira Ide , Masahiro Yamamura , Hideaki Uchida
发明人： Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yuji Yokoyama , Nozomu Matsuzaki , Tatsumi Yamauchi , Yutaka Kobayashi , Nobuyuki Gotou , Akira Ide , Masahiro Yamamura , Hideaki Uchida
IPC分类号： G11C7/10 , G11C8/06 , G11C8/10 , G11C8/18 , H03K5/1534 , H03K19/0175 , H03K5/153 , G01R29/02 , H03K3/033
CPC分类号： G11C7/1057 , G11C7/1051 , G11C8/06 , G11C8/10 , G11C8/18 , H03K19/017518 , H03K5/1534
摘要： A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device such as for a memory are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.
摘要翻译：一种半导体器件，其包括以下中的至少一个：（1）由输入电平转换器和非反相缓冲电路构成的输入缓冲电路和各自包括实现高速操作的BiCMOS电路的反相缓冲电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据来自响应于ATD信号的时钟发生器的信号来控制诸如存储器的装置的解码器，读出放大器和输出缓冲器。

8. 发明授权

US5387827A Semiconductor integrated circuit having logic gates 失效
标题翻译：具有逻辑门的半导体集成电路
公开(公告)号：US5387827A
公开(公告)日：1995-02-07
申请号：US643372
申请日：1991-01-22
申请人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
发明人： Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
IPC分类号： G11C7/10 , G11C8/10 , H03K19/0948 , H03K19/23
CPC分类号： H03K19/0948 , G11C7/1051 , G11C7/1078 , G11C8/10
摘要： A semiconductor integrated logic circuit is provided which includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, wherein each of the logic gates is coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. This arrangement is particularly effective for decoders in semiconductor memory circuits which use a common NMOS to receive one input for a plurality of logic decoder gates. An improved read/write arrangement is also provided for semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
摘要翻译：提供了一种半导体集成逻辑电路，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入信号的第一输入端，其中每个逻辑门耦合到公共节点。在一个实施例中，第一和第二开关元件也耦合到公共节点。第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。这种布置对于使用公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效。还提供了一种用于半导体存储器电路的改进的读/写布置，其包括在写入操作期间防止公共读取线连接到数据线的电路。这通过在写入期间去除公共读取线的负载来增强写入速度。

9. 发明授权

US09506997B2 Magnetic-field-angle measurement apparatus and rotational-angle measurement apparatus using same 有权
标题翻译：磁场角测量装置和使用其的旋转角度测量装置
公开(公告)号：US09506997B2
公开(公告)日：2016-11-29
申请号：US13697690
申请日：2010-05-14
申请人： Mutsumi Suzuki , Hiroshi Iwasawa , Masahiro Iwamura
发明人： Mutsumi Suzuki , Hiroshi Iwasawa , Masahiro Iwamura
IPC分类号： G01R33/09 , G11C7/06 , H01L43/08
摘要： In a magnetic-field angle detection device and a rotation angle detection device in which the accuracy of the measured angle is not degraded even if the MR ratio of the tunneling magnetoresistance element is increased. In a magnetic-field-angle measurement apparatus including a magnetic-field-angle detection circuit and a magnetic sensor having a tunneling magnetoresistance element with a pinned magnetic layer, the magnetic-field-angle detection circuit has a power-supply unit that outputs a constant voltage as a bias voltage to the tunneling magnetoresistance element of the magnetic sensor and a current-detection unit that detects an output current of the tunneling magnetoresistance element. The accuracy of the measured angle of the magnetic-field angle detection device and the rotation angle detection device is improved by measuring the tunneling magnetoresistance element current while maintaining the terminal voltage of the tunneling magnetoresistance element constant with input impedance of the current-detection unit as zero.
摘要翻译：在磁场角检测装置和旋转角度检测装置中，即使隧道磁阻元件的MR比增加，测量角度的精度也不会降低。在包括磁场角检测电路的磁场角测量装置和具有钉扎磁性层的隧道磁阻元件的磁传感器中，磁场角检测电路具有电源单元，其输出恒定电压作为磁传感器的隧道磁阻元件的偏置电压，以及电流检测单元，其检测隧道磁阻元件的输出电流。通过测量隧道磁阻元件电流来改善磁场角检测装置和旋转角度检测装置的测量角度的精度，同时保持隧道磁阻元件的端电压恒定，电流检测单元的输入阻抗为零。

10. 发明申请

US20060158162A1 MOS rectifying device, driving method thereof, and motor generator and motor vehicle using thereof 失效
公开(公告)号：US20060158162A1
公开(公告)日：2006-07-20
申请号：US11206225
申请日：2005-08-18
申请人： Masamitsu Inaba , Shinji Shirakawa , Masahiro Iwamura
发明人： Masamitsu Inaba , Shinji Shirakawa , Masahiro Iwamura
IPC分类号： G05F1/40 , G05F1/455
CPC分类号： H02M7/219 , H02P9/30 , H02P2101/45
摘要： V-phase upper-arm open phase detecting circuit outputs a permission signal to allow U-phase lower-arm MOSFET to be conductive when the V-phase voltage is higher than the positive electrode potential. In response to this permission signal, U-phase lower-arm driver circuit drives U-phase lower-arm MOSFET. V-phase lower-arm open phase detecting circuit outputs a permission signal to allow U-phase upper-arm MOSFET to be conductive when the V-phase voltage is lower than the negative electrode potential. In response to this permission signal, U-phase upper-arm driver circuit drives U-phase upper-arm MOSFET. Thereby, a MOS rectifying device capable of rectifying even when an open phase occurs, a driving method thereof, and a motor vehicle using thereof can be provided.

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