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71. 发明申请

US20060054929A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060054929A1
公开(公告)日：2006-03-16
申请号：US10515886
申请日：2004-11-29
申请人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kensuke Kasahara , Yasuhiro Okamoto , Masaaki Kuzuhara
发明人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kensuke Kasahara , Yasuhiro Okamoto , Masaaki Kuzuhara
IPC分类号： H01L31/109
CPC分类号： H01L29/7783 , H01L29/2003
摘要： A semiconductor device includes, on a substrate (101), a buffer layer (102), and an channel layer (104), consisting essentially of semiconductor of a wultzite compound of group III-V, having a (0001) plane as a principal plane. The channel layer is subjected to compressive strain. A carrier supplying layer (103) is interposed between the channel layer (104) and the buffer layer (102). The carrier supplying layer (103) consists essentially of semiconductor of a wultzite compound of group III-V as a main component. N-type impurities are doped into the entire or part of the carrier supplying layer (103).
摘要翻译：半导体器件在衬底（101）上包括缓冲层（102）和沟道层（104），该沟道层（104）主要由具有（0001）面作为主体的III-V族的无丝绒化合物的半导体组成飞机通道层经受压应变。载体供给层（103）插入在沟道层（104）和缓冲层（102）之间。载体供给层（103）主要由作为主要成分的III-V族的无水锰矿化合物的半导体构成。 N型杂质被掺杂到载体供给层（103）的整个或部分中。

72. 发明授权

US06765241B2 Group III nitride semiconductor device of field effect transistor type having reduced parasitic capacitances 失效
标题翻译：具有降低的寄生电容的场效应晶体管类型的III族氮化物半导体器件
公开(公告)号：US06765241B2
公开(公告)日：2004-07-20
申请号：US10362883
申请日：2003-02-27
申请人： Yasuo Ohno , Nobuyuki Hayama , Kensuke Kasahara , Tatsuo Nakayama , Hironobu Miyamoto , Yuji Takahashi , Yuji Ando , Kohji Matsunaga , Masaaki Kuzuhara
发明人： Yasuo Ohno , Nobuyuki Hayama , Kensuke Kasahara , Tatsuo Nakayama , Hironobu Miyamoto , Yuji Takahashi , Yuji Ando , Kohji Matsunaga , Masaaki Kuzuhara
IPC分类号： H01L29812
CPC分类号： H01L29/8126 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L29/045 , H01L29/2003
摘要： A group III nitride semiconductor device of field effect transistor type having improved productivity, reduced parasitic capacitances adapted for excellent device performance in high-speed operation as well as good heat diffusion characteristics. The device includes an epitaxial growth layer of a group III nitride semiconductor with a buffer layer laid under it, formed on an A plane (an (11-20) plane) of a sapphire. Thereon a gate electrode, a source electrode, a drain electrode, and pad electrodes are formed, and a ground conductor layer is formed on the back face of the sapphire substrate. A thickness of said sapphire substrate tsub satisfies the following Equation (1). t sub ≦ 10 ⁢ ϵ sub ⁢ S pad ϵ epi ⁢ S gate ⁢ t act where Spad is an area of the pad electrode; Sgate is an area of the gate electrode; &egr;sub is a relative permittivity of the sapphire substrate in the direction of the thickness; &egr;epi is a relative permittivity of the group III nitride semiconductor layer in the direction of the thickness; tsub is a thickness of the sapphire substrate; and tact is an effective thickness of the group III nitride semiconductor layer.
摘要翻译：具有提高生产率的场效应晶体管类型的III族氮化物半导体器件，适于在高速操作中优异的器件性能以及良好的热扩散特性的减小的寄生电容。该器件包括形成在蓝宝石的A平面（（11-20）面）上的具有缓冲层的III族氮化物半导体的外延生长层。在其上形成栅电极，源电极，漏电极和焊盘电极，并且在蓝宝石衬底的背面上形成接地导体层。所述蓝宝石衬底tsub的厚度满足以下等式（1）。其中，Spad是焊盘电极的面积; Sgate是栅电极的面积; epsilonsub是蓝宝石衬底在厚度方向上的相对介电常数;εilon 是III族氮化物半导体层在厚度方向上的相对介电常数; tsub是蓝宝石衬底的厚度; andtact是III族氮化物半导体层的有效厚度。

73. 发明授权

US06534790B2 Compound semiconductor field effect transistor 有权
标题翻译：复合半导体场效应晶体管
公开(公告)号：US06534790B2
公开(公告)日：2003-03-18
申请号：US09796803
申请日：2001-03-02
申请人： Takehiko Kato , Kazuki Ota , Hironobu Miyamoto , Naotaka Iwata , Masaaki Kuzuhara
发明人： Takehiko Kato , Kazuki Ota , Hironobu Miyamoto , Naotaka Iwata , Masaaki Kuzuhara
IPC分类号： H01L2915
CPC分类号： H01L29/66462 , H01L29/7785
摘要： The present invention provides a field effect transistor (FET) having, on a semi-insulating compound semiconductor substrate, a buffer layer; an active layer that includes a channel layer made of a first conductive-type epitaxial growth layer (e.g. InGaAs); source/drain electrodes formed on a first conductive-type contact layer which is formed either on said active layer or on a lateral face thereof; a gate layer made of a second conductive-type epitaxial growth layer (e.g. p+-GaAs); and a gate electrode formed on said gate layer; which further has, between said second conductive-type gate layer and said channel layer, a semiconductor layer (e.g. InGaP) that rapidly lowers the energy of the valance band spreading from said gate layer to said channel layer. The present invention improves withstand voltage characteristic of a FET having a pn junction in a gate region (JFET) and realizes stable operations of a JFET.
摘要翻译：本发明提供一种在半绝缘化合物半导体衬底上具有缓冲层的场效应晶体管（FET）包括由第一导电型外延生长层（例如InGaAs）制成的沟道层的有源层; 源极/漏极，形成在形成在所述有源层上或其侧面上的第一导电型接触层上; 由第二导电型外延生长层（例如p + -GaAs）制成的栅极层; 以及形成在所述栅极层上的栅电极; 在所述第二导电型栅极层和所述沟道层之间还具有快速降低从所述栅极层扩散到所述沟道层的能带的能量的半导体层（例如InGaP）。本发明提高了在栅极区（JFET）中具有pn结的FET的耐压特性，并且实现了JFET的稳定操作。

74. 发明授权

US06492669B2 Semiconductor device with schottky electrode having high schottky barrier 有权
标题翻译：肖特基电极具有高肖特基势垒的半导体器件
公开(公告)号：US06492669B2
公开(公告)日：2002-12-10
申请号：US09892567
申请日：2001-06-28
申请人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kazuaki Kunihiro , Yuji Takahashi , Kensuke Kasahara , Nobuyuki Hayama , Yasuo Ohno , Kouji Matsunaga , Masaaki Kuzuhara
发明人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kazuaki Kunihiro , Yuji Takahashi , Kensuke Kasahara , Nobuyuki Hayama , Yasuo Ohno , Kouji Matsunaga , Masaaki Kuzuhara
IPC分类号： H01L2980
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/2003 , H01L29/475 , H01L29/7783
摘要： A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.
摘要翻译：在具有缓冲层的半导体器件的基板上形成载流子行进层，然后在该载体行进层上形成间隔层和载体供给层。在载体供给层上设置有源电极和漏电极，在插入的肖特基层上设置有栅电极。载体供应层由AlGaN组成并具有拉伸应变。肖特基层由InGaN组成并具有压应变。在肖特基层的载流子供给层侧感应出负的压电电荷，在肖特基层的相反侧产生正的压电电荷，由此获得足够的肖特基势垒高度，并且抑制泄漏电流。

75. 发明授权

US5608239A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US5608239A
公开(公告)日：1997-03-04
申请号：US357216
申请日：1994-12-13
申请人： Hironobu Miyamoto , Tatsuo Nakayama
发明人： Hironobu Miyamoto , Tatsuo Nakayama
IPC分类号： H01L29/812 , H01L21/338 , H01L29/778 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/7783
摘要： The present invention relates to a field effect transistor with high speed and excellent high frequency characteristics. A hetero junction field effect transistor, comprising a first semiconductor layer that contains In, a second semiconductor layer that contains In whose composition ratio is smaller than that of the first semiconductor layer, and a third semiconductor layer whose electron affinity is smaller than that of the first semiconductor layer, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are successively disposed in the order, and wherein the thickness of the second semiconductor layer is equal to or larger than the thickness of two monolayers thereof and less than 4 nm. A current of this field effect transistor flows in the first semiconductor layer 3 and the second semiconductor layer 4 of the transistor. When the thickness of the second semiconductor layer 4 is 4 nm or more, the ratio of electrons that exist in the first semiconductor layer 3 is 85% or less of the case that the thickness of the second semiconductor layer 4 is almost zero. Thus, when the thickness of the second semiconductor layer 4 is decreased to the thickness of two monolayers thereof, the ratio of electrons that exist in the first semiconductor layer 3 becomes nearly 100%. Consequently, the high frequency characteristics of the transistor are improved.
摘要翻译：本发明涉及具有高速度和优异的高频特性的场效应晶体管。一种异质结场效应晶体管，包括含有In的第一半导体层，包含其组成比小于第一半导体层的组成比的第二半导体层，以及第三半导体层，其电子亲和力小于第一半导体层，其中第一半导体层，第二半导体层和第三半导体层依次依次布置，并且其中第二半导体层的厚度等于或大于其两个单层的厚度和更小的厚度超过4nm。该场效应晶体管的电流在晶体管的第一半导体层3和第二半导体层4中流动。当第二半导体层4的厚度为4nm以上时，在第二半导体层4的厚度几乎为零的情况下，存在于第一半导体层3中的电子的比例为85％以下。因此，当第二半导体层4的厚度减小到其两个单层的厚度时，存在于第一半导体层3中的电子的比例接近100％。因此，提高了晶体管的高频特性。

76. 发明授权

US5536358A Method of estimating etching damage 失效
标题翻译：估算蚀刻损伤的方法
公开(公告)号：US5536358A
公开(公告)日：1996-07-16
申请号：US307236
申请日：1994-09-16
申请人： Kazuaki Ashizuka , Hironobu Miyamoto
发明人： Kazuaki Ashizuka , Hironobu Miyamoto
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/66 , H01L21/00
CPC分类号： H01L22/12
摘要： The invention provides a method of estimating damage which a semiconductor substrate has suffered in a dry etching step included in a semiconductor fabricating step. The invention includes the steps of forming a delta-doped donor layer at a predetermined depth measuring from a surface of the semiconductor, measuring electron concentrations of the semiconductor before and after the dry etching step, and calculating a difference between the delta-doped donor concentrations to thereby quantitatively estimate a distribution of the damage throughout the depth of the semiconductor.
摘要翻译：本发明提供了一种在半导体制造步骤中包括的干蚀刻步骤中估计半导体衬底遭受的损坏的方法。本发明包括以下步骤：在从半导体表面测量的预定深度处形成δ-掺杂的施主层，测量干蚀刻步骤之前和之后的半导体的电子浓度，以及计算δ-掺杂的供体浓度从而定量估计半导体整个深度的损伤分布。

77. 发明授权

US5364499A Dry etching process for gallium arsenide excellent in selectivity with respect to aluminum gallium arsenide 失效
标题翻译：砷化镓的干蚀刻工艺对于砷化镓砷的选择性优异
公开(公告)号：US5364499A
公开(公告)日：1994-11-15
申请号：US811679
申请日：1991-12-23
申请人： Hironobu Miyamoto
发明人： Hironobu Miyamoto
IPC分类号： H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/00
CPC分类号： H01L21/30621
摘要： A dry etching process achieves an excellent selectivity between aluminum gallium arsenide and gallium arsenide, and gaseous mixture containing chlorine and sulfur hexafluoride is used as an etchant for selectively etching the gallium arsenide with respect to the aluminum gallium arsenide without sacrifice of the controllability of the dry etching system as well as of the environment.
摘要翻译：干蚀刻工艺在砷化铝镓和砷化镓之间实现优异的选择性，并且使用含有氯和六氟化硫的气体混合物作为蚀刻剂，用于相对于砷化镓砷选择性地蚀刻砷化镓，而不牺牲干燥的可控性蚀刻系统以及环境。

78. 发明授权

US08659055B2 Semiconductor device, field-effect transistor, and electronic device 有权
标题翻译：半导体器件，场效应晶体管和电子器件
公开(公告)号：US08659055B2
公开(公告)日：2014-02-25
申请号：US13497557
申请日：2010-06-16
申请人： Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Hironobu Miyamoto , Tatsuo Nakayama , Yuji Ando
发明人： Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Hironobu Miyamoto , Tatsuo Nakayama , Yuji Ando
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/1054 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/267 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/66734
摘要： Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon.A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4. The gate electrode 12 is in contact with an upper surface of the first n-type semiconductor layer 2, side surfaces of the p-type semiconductor layer 3, and side surfaces of the second n-type semiconductor layer 4 at inner surfaces of the opening portion to be filled or a surface of the notched portion via the gate insulation film 21. The p-type semiconductor layer 3 has a positive polarization charge at a first n-type semiconductor layer 2 side in a state where a voltage is applied to none of the electrodes.
摘要翻译：提供能够抑制穿通现象发生的半导体装置。半导体器件包括衬底1，第一n型半导体层2，p型半导体层3，第二n型半导体层4，漏极13，源电极11，栅电极12和栅极绝缘膜21，其中第一n型半导体层2，p型半导体层3和第二n型半导体层4依次层压在基板1上。漏电极13与第一n型半导体层2欧姆接触。源电极11与第二n型半导体层4欧姆接触。要填充的开口部分或延伸的缺口部分从第二n型半导体层4的上表面到第一n型半导体层2的上部形成在p型半导体层3的一部分上，第二n型半导体层的一部分栅电极12与第一n型半导体层2的上表面，p型半导体层3的侧表面和第二n型半导体层4的内表面的侧表面接触待填充的开口部分或经由栅极绝缘膜21的切口部分的表面。在施加电压的状态下，p型半导体层3在第一n型半导体层2侧具有正极化电荷没有电极。

79. 发明授权

US08552471B2 Semiconductor apparatus having reverse blocking characteristics and method of manufacturing the same 失效
标题翻译：具有反向阻挡特性的半导体装置及其制造方法
公开(公告)号：US08552471B2
公开(公告)日：2013-10-08
申请号：US13139789
申请日：2009-12-11
申请人： Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Kazuki Ota , Takashi Inoue , Hironobu Miyamoto , Kazuomi Endo
发明人： Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Kazuki Ota , Takashi Inoue , Hironobu Miyamoto , Kazuomi Endo
IPC分类号： H01L29/66
CPC分类号： H01L29/402 , H01L29/0619 , H01L29/2003 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/7787
摘要： There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.
摘要翻译：提供了能够实现反向阻挡特性和低导通电阻的半导体装置。半导体装置包括：第一半导体层，包括沟道层，形成在第一半导体层上的源电极，在第一半导体层上与源极间隔一定距离处形成的漏电极，以及形成在源电极和第一半导体层上的漏电极。漏电极包括第一漏极区，其中第一半导体层和第一漏极区之间的反向电流被阻挡，以及形成在比栅极电极比第一漏极区更远的距离处的第二漏区，半导体层和第二漏极区域比第一半导体层和第一漏极区域之间的电阻低。

80. 发明授权

US08395237B2 Group nitride bipolar transistor 有权
标题翻译：组氮化物双极晶体管
公开(公告)号：US08395237B2
公开(公告)日：2013-03-12
申请号：US13124872
申请日：2009-10-16
申请人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
发明人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
IPC分类号： H01L29/66 , H01L29/737
CPC分类号： H01L29/7371 , H01L29/045 , H01L29/2003
摘要： A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [0001] direction of the substrate. The first nitride semiconductor includes: InycAlxcGa1-xc-ycN (0≦xc≦1, 0≦yc≦1, 0
摘要翻译：双极晶体管包括：基板; 具有p导电型的集电极和基极层，具有n导电型的发射极层。集电极层形成在衬底上方并且包括第一氮化物半导体。具有p型导电型的基底层形成在集电极层上，并且包括第二耐磨半导体。具有n导电型的发射极层形成在基极层上并且包括第三氮化物半导体。形成集电体层，基极层和发射极层，使得相对于基板的表面的晶体生长方向与基板的[0001]方向平行。第一氮化物半导体包括：InycAlxcGa1-xc-ycN（0＆nlE; xc＆nlE; 1,0＆amp; nlE; yc＆nlE; 1,0

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