专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08981434B2 Semiconductor device and field effect transistor 有权
标题翻译：半导体器件和场效应晶体管
公开(公告)号：US08981434B2
公开(公告)日：2015-03-17
申请号：US13393002
申请日：2010-06-23
申请人： Hironobu Miyamoto , Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Kazuomi Endo
发明人： Hironobu Miyamoto , Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Kazuomi Endo
IPC分类号： H01L29/76 , H01L29/812 , H01L29/201 , H01L29/78 , H01L29/06 , H01L29/20 , H01L29/205 , H01L29/417 , H01L29/423
CPC分类号： H01L29/8122 , H01L29/0657 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/7809 , H01L29/7812 , H01L29/7813 , H01L29/8128
摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased. A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.
摘要翻译：提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

2. 发明授权

US08921894B2 Field effect transistor, method for producing the same, and electronic device 有权
标题翻译：场效应晶体管，其制造方法和电子器件
公开(公告)号：US08921894B2
公开(公告)日：2014-12-30
申请号：US13637555
申请日：2010-12-15
申请人： Yuji Ando , Takashi Inoue , Kazuki Ota , Yasuhiro Okamoto , Tatsuo Nakayama , Kazuomi Endo
发明人： Yuji Ando , Takashi Inoue , Kazuki Ota , Yasuhiro Okamoto , Tatsuo Nakayama , Kazuomi Endo
IPC分类号： H01L29/778 , H01L21/8252 , H01L29/78 , H01L29/20 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78 , H01L21/8252 , H01L29/2003 , H01L29/4232 , H01L29/66477 , H01L29/7785 , H01L29/7787
摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.
摘要翻译：本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面为III族原子平面垂直于（0001）晶轴。栅格弛豫缓冲层112，具有压缩应变的沟道层113和具有拉伸应变的阻挡层114以及具有压缩应变的间隔层115以此顺序层压在基板100上。栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

3. 发明授权

US08674409B2 Heterojunction field effect transistor, method for producing heterojunction field effect transistor, and electronic device 有权
标题翻译：异质结场效应晶体管，异质结场效应晶体管的制造方法和电子器件
公开(公告)号：US08674409B2
公开(公告)日：2014-03-18
申请号：US13141449
申请日：2009-12-25
申请人： Takashi Inoue , Hironobu Miyamoto , Kazuki Ota , Tatsuo Nakayama , Yasuhiro Okamoto , Yuji Ando
发明人： Takashi Inoue , Hironobu Miyamoto , Kazuki Ota , Tatsuo Nakayama , Yasuhiro Okamoto , Yuji Ando
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L29/0843 , H01L29/2003 , H01L29/41766 , H01L29/42316 , H01L29/66462
摘要： A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided. In the heterojunction field effect transistor, an electron transit layer 11 formed of a III-nitride semiconductor is formed on a substrate 10, an electron supply layer 12 formed of a III-nitride semiconductor forms a heterojunction with an upper surface of the electron transit layer 11, a gate electrode 14, a source electrode 15A, and a drain electrode 15B are arranged on the electron supply layer 12, n-type conductive layer regions 13A and 13B each extended from an upper part of the electron transit layer 11 to an upper surface of the electron supply layer 12 are provided in at least a part below the source electrode 15A and a part below the drain electrode 15B, and an n-type impurity concentration at a heterojunction interface of an electron transit layer 11 part of each of the n-type conductive layer regions 13A and 13B with the electron supply layer 12 is 1×1020 cm−3 or more.
摘要翻译：提供具有低访问阻抗，低导通电阻等的异质结场效应晶体管，提供了异质结场效应晶体管和电子器件的制造方法。在异质结场效应晶体管中，在衬底10上形成由III族氮化物半导体形成的电子迁移层11，由III族氮化物半导体形成的电子供给层12与电子迁移层的上表面形成异质结如图11所示，在电子供给层12上配置有栅电极14，源电极15A和漏电极15B，从电子渡越层11的上部延伸到上部的n型导电层区域13A，13B 电子供给层12的表面设置在源电极15A的下方以及漏电极15B的下方的至少一部分以及电子迁移层11的异质界面的n型杂质浓度具有电子供给层12的n型导电层区域13A，13B为1×1020cm-3以上。

4. 发明申请

US20130099245A1 FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC DEVICE 审中-公开
标题翻译：场效应晶体管，其制造方法和电子器件
公开(公告)号：US20130099245A1
公开(公告)日：2013-04-25
申请号：US13637316
申请日：2010-12-15
申请人： Yuji Ando , Takashi Inoue , Kazuki Ota , Yasuhiro Okamoto , Tatsuo Nakayama , Kazuomi Endo
发明人： Yuji Ando , Takashi Inoue , Kazuki Ota , Yasuhiro Okamoto , Tatsuo Nakayama , Kazuomi Endo
IPC分类号： H01L29/205 , H01L29/66 , H01L29/78
CPC分类号： H01L29/205 , H01L29/2003 , H01L29/4232 , H01L29/66431 , H01L29/7785 , H01L29/7787 , H01L29/78
摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the lattice-relaxed channel layer 113, and the barrier layer 114 having a tensile strain, and the spacer layer 115 are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.
摘要翻译：本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面为III族原子平面垂直于（0001）晶轴。晶格弛豫缓冲层112，晶格松弛沟道层113和具有拉伸应变的势垒层114和间隔层115依次层压在基板100上。栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

5. 发明申请

US20120217547A1 FIELD EFFECT TRANSISTOR WITH REDUCED GATE LEAKAGE CURRENT 有权
标题翻译：具有降低栅极泄漏电流的场效应晶体管
公开(公告)号：US20120217547A1
公开(公告)日：2012-08-30
申请号：US13468373
申请日：2012-05-10
申请人： Yuji ANDO , Hironobu MIYAMOTO , Tatsuo NAKAYAMA , Yasuhiro OKAMOTO , Takashi INOUE , Yasuhiro MURASE , Kazuki OTA , Akio WAKEJIMA , Naotaka KURODA
发明人： Yuji ANDO , Hironobu MIYAMOTO , Tatsuo NAKAYAMA , Yasuhiro OKAMOTO , Takashi INOUE , Yasuhiro MURASE , Kazuki OTA , Akio WAKEJIMA , Naotaka KURODA
IPC分类号： H01L29/778
CPC分类号： H01L29/7787 , H01L29/2003
摘要： Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x
摘要翻译：公开了一种HJFET 110，其包括：由In y Ga 1-y N（0＆lt; n 1; y＆n 1; 1）构成的沟道层12; 载体供给层13由Al x Ga 1-x N（0＆lt; n 1; x＆n 1; 1）组成，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10 11× NA×＆eegr×T [cm-2] <5.6×1013x，其中x表示所述载体供给层的Al组成比，t表示所述p型层的厚度，NA表示杂质浓度，＆eegr; 表示活化比。

6. 发明申请

US20120199889A1 SEMICONDUCTOR DEVICE AND FIELD EFFECT TRANSISTOR 有权
标题翻译：半导体器件和场效应晶体管
公开(公告)号：US20120199889A1
公开(公告)日：2012-08-09
申请号：US13393002
申请日：2010-06-23
申请人： Hironobu Miyamoto , Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Kazuomi Endo
发明人： Hironobu Miyamoto , Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Kazuomi Endo
IPC分类号： H01L29/78
CPC分类号： H01L29/8122 , H01L29/0657 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/7809 , H01L29/7812 , H01L29/7813 , H01L29/8128
摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased.A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.
摘要翻译：提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

7. 发明授权

US08198652B2 Field effect transistor with reduced gate leakage current 有权
标题翻译：具有减小栅极漏电流的场效应晶体管
公开(公告)号：US08198652B2
公开(公告)日：2012-06-12
申请号：US12295004
申请日：2007-03-29
申请人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Yasuhiro Murase , Kazuki Ota , Akio Wakejima , Naotaka Kuroda
发明人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Yasuhiro Murase , Kazuki Ota , Akio Wakejima , Naotaka Kuroda
IPC分类号： H01L29/80
CPC分类号： H01L29/7787 , H01L29/2003
摘要： Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x
摘要翻译：公开了一种HJFET 110，其包括：由In y Ga 1-y N（0＆lt; n 1; y＆n 1; 1）构成的沟道层12; 载体供给层13由Al x Ga 1-x N（0＆lt; n 1; x＆n 1; 1）组成，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10 11× NA×＆eegr×T [cm-2] <5.6×1013x，其中x表示载流子供应层的Al组成比，t表示p型层的厚度，NA表示杂质浓度，＆eegr; 表示活化比。

8. 发明申请

US20110278586A1 BIPOLAR TRANSISTOR 有权
标题翻译：双极晶体管
公开(公告)号：US20110278586A1
公开(公告)日：2011-11-17
申请号：US13124873
申请日：2009-10-16
申请人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
发明人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
IPC分类号： H01L29/20
CPC分类号： H01L29/7371 , H01L29/0649 , H01L29/0817 , H01L29/0821 , H01L29/2003 , H01L29/205 , H01L29/475 , H01L29/66318
摘要： A bipolar transistor is provided with an emitter layer, a base layer and a collector layer. The emitter layer is formed above a substrate and is an n-type conductive layer including a first nitride semiconductor. The base layer is formed on the emitter layer and is a p-type conductive including a second nitride semiconductor. The collector layer is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed such that a crystal growth direction to the substrate surface is parallel to a substrate direction of [000-1]. The third nitride semiconductor contains InycAlxcGa1-xc-ycN (0•xc•1, 0•yc•1, 0
摘要翻译：双极晶体管设置有发射极层，基极层和集电极层。发射极层形成在衬底之上，并且是包括第一氮化物半导体的n型导电层。基极层形成在发射极层上，是包含第二氮化物半导体的p型导体。集电极层形成在基极层上并且包括第三氮化物半导体。形成集电体层，基极层和发射极层，使得到基板表面的晶体生长方向平行于[000-1]的基板方向。第三氮化物半导体含有InycAlxcGa1-xc-ycN（0·xc·1,0,0·yc·1,0,0cc·yc·1）。第三氮化物半导体中的表面侧的a轴长度比基板侧的a轴长短。

9. 发明申请

US20100276732A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20100276732A1
公开(公告)日：2010-11-04
申请号：US12810096
申请日：2008-12-25
申请人： Yuji Ando , Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Tatsuo Nakayama , Hironobu Miyamoto
发明人： Yuji Ando , Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Tatsuo Nakayama , Hironobu Miyamoto
IPC分类号： H01L29/78
CPC分类号： H01L29/66462 , H01L27/0605 , H01L29/0891 , H01L29/2003 , H01L29/4232 , H01L29/7781
摘要： A semiconductor device includes a lower barrier layer 12 composed of a layer of AlxGa1-xN (0≦x≦1) in a state of strain relaxation, and a channel layer 13, which is composed of a layer of InyGa1-yN (0≦y≦1) disposed on the lower barrier layer 12, has band gap that is smaller than band gap of the lower barrier layer 12, and exhibits compressive strain. A gate electrode 1G is formed over the channel layer 13 via an insulating film 15 and a source electrode 1S and a drain electrode 1D serving as ohmic electrodes are formed over the channel layer 13. The insulating film 15 is constituted of polycrystalline or amorphous member.
摘要翻译：半导体器件包括在应变松弛的状态下由Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）层构成的下阻挡层12，以及由In y Ga 1-y N（0＆lt; nlE; 1）层组成的沟道层13。 y）; 1）设置在下阻挡层12上，具有小于下阻挡层12的带隙的带隙，并且表现出压缩应变。在沟道层13上经由绝缘膜15形成栅极电极1G，在沟道层13上形成有用作欧姆电极的源电极1S和漏电极1D。绝缘膜15由多晶或非晶构成。

10. 发明申请

US20090230430A1 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US20090230430A1
公开(公告)日：2009-09-17
申请号：US11921857
申请日：2006-06-12
申请人： Hironobu Miyamoto , Yuji Ando , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Aklo Wakejima , Kensuke Kasahara , Yasuhiro Murase , Kohji Matsunaga , Katsumi Yamanoguchi , Hidenori Shimawaki
发明人： Hironobu Miyamoto , Yuji Ando , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Aklo Wakejima , Kensuke Kasahara , Yasuhiro Murase , Kohji Matsunaga , Katsumi Yamanoguchi , Hidenori Shimawaki
IPC分类号： H01L29/78
CPC分类号： H01L29/404 , H01L29/7783 , H01L29/7787 , H01L29/802 , H01L29/812
摘要： A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (113), is designated as Lol, and the gate length is Lg, the relation expressed as 0≦Lol/Lg≦1 holds.
摘要翻译：场效应晶体管包括由设置在由GaAs或InP制成的半导体衬底（110）上的化合物半导体（111）作为操作层的层结构，并且采用第一场极板电极（116）和第二场极板电极（118）。第二场板电极包括位于第一场极板电极和漏电极（114）之间的区域中的屏蔽部分（119），用于屏蔽第一场极板电极与漏极电极。当在栅极长度方向的截面图中，重叠区域的栅极长度方向上的长度，其中第二场极板电极与由第一场极板电极和栅电极构成的结构的上部重叠（113）表示为Lol，栅极长度为Lg，表示为0 <= Lol / Lg <= 1的关系成立。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式