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1. 发明公开

US20230331507A1 MEDIUM PROCESSING APPARATUS AND IMAGE FORMING SYSTEM INCORPORATING SAME 审中-公开
公开(公告)号：US20230331507A1
公开(公告)日：2023-10-19
申请号：US18300766
申请日：2023-04-14
申请人： Kazuki Ota , Yohei Yamazaki , Yuji Miyachi , Yusuke Hirono , Yuta Yanai , Yuji Susaki , Masanobu Kimata
发明人： Kazuki Ota , Yohei Yamazaki , Yuji Miyachi , Yusuke Hirono , Yuta Yanai , Yuji Susaki , Masanobu Kimata
IPC分类号： B65H37/04 , B65H39/10
CPC分类号： B65H37/04 , B65H39/10 , B65H2403/40 , B65H2301/1635 , B65H2301/51611 , B65H2408/1223 , B65H2801/27
摘要： A medium processing apparatus includes a conveyor, a tray, a binder, a mover, and a switcher. The switcher includes a first passage, a second passage, and a movable wall. The movable wall guides a guided portion of the binder to the second passage when the guided portion moving along the first passage from an end side to a center side contacts the movable wall; causes the guided portion to pass when the guided portion moving along the second passage from the end side to the center side contacts the movable wall; guides the guided portion to the first passage when the guided portion moving along the second passage from the center side to the end side contacts the movable wall; and causes the guided portion to pass when the guided portion moving along the first passage from the center side to the end side contacts the movable wall.

2. 发明授权

US08928038B2 Field effect transistor containing a group III nitride semiconductor as main component 有权
标题翻译：含有III族氮化物半导体作为主要成分的场效应晶体管
公开(公告)号：US08928038B2
公开(公告)日：2015-01-06
申请号：US14117763
申请日：2012-05-15
申请人： Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota
发明人： Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota
IPC分类号： H01L29/66 , H01L29/778 , H01L29/205 , H01L29/20 , H01L29/423 , H01L29/51
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7786
摘要： A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1-zAlzN (0≦z≦1), a channel layer having a composition of: AlxGa1-xN (0≦x≦1) or InyGa1-yN (0≦y≦1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.
摘要翻译：场效应晶体管包括衬底和设置在衬底上的半导体层，其中半导体层包括设置在衬底上的下阻挡层，生长Ga面，晶格弛豫并具有组成In 1-z Al z N（0＆nl; z＆nl E; 1），具有以下组成的沟道层：Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）或In y Ga 1-y N（0＆nlE; y＆nlE; 1）。或提供在栅极绝缘膜上并与栅极绝缘膜配置的栅电极，栅极配置在栅极绝缘膜上，栅电极配置在栅极绝缘膜上，位于源电极和漏电极之间的区域。

3. 发明授权

US08680580B2 Field effect transistor and process for manufacturing same 有权
标题翻译：场效应晶体管及其制造方法相同
公开(公告)号：US08680580B2
公开(公告)日：2014-03-25
申请号：US12742587
申请日：2008-11-17
申请人： Kazuki Ota
发明人： Kazuki Ota
IPC分类号： H01L21/02 , H01L29/66 , H01L29/15 , H01L31/0256
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/66462
摘要： A field effect transistor includes: a channel layer 103 containing GaN or InGaN; a first electron-supplying layer 104 disposed over the channel layer 103 and containing InxAlyGa1-x-yN (0≦x
摘要翻译：场效应晶体管包括：包含GaN或InGaN的沟道层103; 第一电子供应层104设置在沟道层103上并且包含In x Al y Ga 1-x-y N（0＆nl E; x <1,0

4. 发明授权

US08659055B2 Semiconductor device, field-effect transistor, and electronic device 有权
标题翻译：半导体器件，场效应晶体管和电子器件
公开(公告)号：US08659055B2
公开(公告)日：2014-02-25
申请号：US13497557
申请日：2010-06-16
申请人： Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Hironobu Miyamoto , Tatsuo Nakayama , Yuji Ando
发明人： Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Hironobu Miyamoto , Tatsuo Nakayama , Yuji Ando
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/1054 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/267 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/66734
摘要： Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon.A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4. The gate electrode 12 is in contact with an upper surface of the first n-type semiconductor layer 2, side surfaces of the p-type semiconductor layer 3, and side surfaces of the second n-type semiconductor layer 4 at inner surfaces of the opening portion to be filled or a surface of the notched portion via the gate insulation film 21. The p-type semiconductor layer 3 has a positive polarization charge at a first n-type semiconductor layer 2 side in a state where a voltage is applied to none of the electrodes.
摘要翻译：提供能够抑制穿通现象发生的半导体装置。半导体器件包括衬底1，第一n型半导体层2，p型半导体层3，第二n型半导体层4，漏极13，源电极11，栅电极12和栅极绝缘膜21，其中第一n型半导体层2，p型半导体层3和第二n型半导体层4依次层压在基板1上。漏电极13与第一n型半导体层2欧姆接触。源电极11与第二n型半导体层4欧姆接触。要填充的开口部分或延伸的缺口部分从第二n型半导体层4的上表面到第一n型半导体层2的上部形成在p型半导体层3的一部分上，第二n型半导体层的一部分栅电极12与第一n型半导体层2的上表面，p型半导体层3的侧表面和第二n型半导体层4的内表面的侧表面接触待填充的开口部分或经由栅极绝缘膜21的切口部分的表面。在施加电压的状态下，p型半导体层3在第一n型半导体层2侧具有正极化电荷没有电极。

5. 发明授权

US08552471B2 Semiconductor apparatus having reverse blocking characteristics and method of manufacturing the same 失效
标题翻译：具有反向阻挡特性的半导体装置及其制造方法
公开(公告)号：US08552471B2
公开(公告)日：2013-10-08
申请号：US13139789
申请日：2009-12-11
申请人： Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Kazuki Ota , Takashi Inoue , Hironobu Miyamoto , Kazuomi Endo
发明人： Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Kazuki Ota , Takashi Inoue , Hironobu Miyamoto , Kazuomi Endo
IPC分类号： H01L29/66
CPC分类号： H01L29/402 , H01L29/0619 , H01L29/2003 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/7787
摘要： There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.
摘要翻译：提供了能够实现反向阻挡特性和低导通电阻的半导体装置。半导体装置包括：第一半导体层，包括沟道层，形成在第一半导体层上的源电极，在第一半导体层上与源极间隔一定距离处形成的漏电极，以及形成在源电极和第一半导体层上的漏电极。漏电极包括第一漏极区，其中第一半导体层和第一漏极区之间的反向电流被阻挡，以及形成在比栅极电极比第一漏极区更远的距离处的第二漏区，半导体层和第二漏极区域比第一半导体层和第一漏极区域之间的电阻低。

6. 发明申请

US20130113028A2 SEMICONDUCTOR DEVICE AND FIELD EFFECT TRANSISTOR 有权
标题翻译：半导体器件和场效应晶体管
公开(公告)号：US20130113028A2
公开(公告)日：2013-05-09
申请号：US13393002
申请日：2010-06-23
申请人： Hironobu MIYAMOTO , Yasuhiro OKAMOTO , Yuji ANDO , Tatsuo NAKAYAMA , Takashi INOUE , Kazuki OTA , Kazuomi ENDO
发明人： Hironobu MIYAMOTO , Yasuhiro OKAMOTO , Yuji ANDO , Tatsuo NAKAYAMA , Takashi INOUE , Kazuki OTA , Kazuomi ENDO
IPC分类号： H01L29/78
CPC分类号： H01L29/8122 , H01L29/0657 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/7809 , H01L29/7812 , H01L29/7813 , H01L29/8128
摘要： A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.
摘要翻译：半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

7. 发明申请

US20130105811A1 FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC DEVICE 有权
标题翻译：场效应晶体管，其制造方法和电子器件
公开(公告)号：US20130105811A1
公开(公告)日：2013-05-02
申请号：US13637555
申请日：2010-12-15
申请人： Yuji Ando , Takashi Inoue , Kazuki Ota , Yasuhiro Okamoto , Tatsuo Nakayama , Kazuomi Endo
发明人： Yuji Ando , Takashi Inoue , Kazuki Ota , Yasuhiro Okamoto , Tatsuo Nakayama , Kazuomi Endo
IPC分类号： H01L29/78 , H01L29/66 , H01L29/20
CPC分类号： H01L29/78 , H01L21/8252 , H01L29/2003 , H01L29/4232 , H01L29/66477 , H01L29/7785 , H01L29/7787
摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.
摘要翻译：本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面分别为III族原子平面垂直于（0001）晶轴。栅格弛豫缓冲层112，具有压缩应变的沟道层113和具有拉伸应变的阻挡层114以及具有压缩应变的间隔层115以此顺序层压在基板100上。栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

8. 发明授权

US08395237B2 Group nitride bipolar transistor 有权
标题翻译：组氮化物双极晶体管
公开(公告)号：US08395237B2
公开(公告)日：2013-03-12
申请号：US13124872
申请日：2009-10-16
申请人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
发明人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
IPC分类号： H01L29/66 , H01L29/737
CPC分类号： H01L29/7371 , H01L29/045 , H01L29/2003
摘要： A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [0001] direction of the substrate. The first nitride semiconductor includes: InycAlxcGa1-xc-ycN (0≦xc≦1, 0≦yc≦1, 0
摘要翻译：双极晶体管包括：基板; 具有p导电型的集电极和基极层，具有n导电型的发射极层。集电极层形成在衬底上方并且包括第一氮化物半导体。具有p型导电型的基底层形成在集电极层上，并且包括第二耐磨半导体。具有n导电型的发射极层形成在基极层上并且包括第三氮化物半导体。形成集电体层，基极层和发射极层，使得相对于基板的表面的晶体生长方向与基板的[0001]方向平行。第一氮化物半导体包括：InycAlxcGa1-xc-ycN（0＆nlE; xc＆nlE; 1,0＆amp; nlE; yc＆nlE; 1,0

9. 发明申请

US20110291160A1 FIELD EFFECT TRANSISTOR 有权
标题翻译：场效应晶体管
公开(公告)号：US20110291160A1
公开(公告)日：2011-12-01
申请号：US13147676
申请日：2010-02-03
申请人： Kazuki Ota , Yasuhiro Okamoto , Hironobu Miyamoto
发明人： Kazuki Ota , Yasuhiro Okamoto , Hironobu Miyamoto
IPC分类号： H01L29/778
CPC分类号： H01L29/4236 , H01L29/1029 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/66621 , H01L29/7783 , H01L29/7787
摘要： A field effect transistor includes a nitride-based semiconductor multi-layer structure, a source electrode (108), a drain electrode (109), a protective film (110), and a gate electrode (112) that is provided in a recess structure, which is formed by etching, directly or with a gate insulating film interposed therebetween. The nitride-based semiconductor multi-layer structure includes at least a base layer (103) made of AlXGa1-XN (0≦1), a channel layer (104) made of GaN or InGaN, a first electron supply layer (105), which is an undoped or n-type AlYGa1-YN layer, a threshold value control layer (106), which is an undoped AlZGa1-ZN layer, and a second electron supply layer (107), which is an undoped or n-type AlWGa1-WN layer, epitaxially grown in this order on a substrate (101) with a buffer layer (102) interposed therebetween. The Al composition of each layer in the nitride-based semiconductor multi-layer structure satisfies 0
摘要翻译：场效应晶体管包括氮化物基半导体多层结构，源电极（108），漏电极（109），保护膜（110）和设置在凹槽结构中的栅电极（112），其通过蚀刻直接形成，或者在其间插入栅极绝缘膜。所述氮化物系半导体多层结构至少包括由Al x Ga 1-x N（0＆lt; n 1; 1）构成的基极层（103），由GaN或InGaN构成的沟道层（104），第1电子供给层（105）其是未掺杂的或n型AlYGa1-YN层，作为未掺杂的AlZGa1-ZN层的阈值控制层（106）和作为未掺杂的或n型AlWGa1的第二电子供给层（107） -WN层，在衬底（101）上依次外延生长，缓冲层（102）插入其间。氮化物系半导体多层结构中的各层的Al组成满足0

10. 发明申请

US20110260217A1 SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20110260217A1
公开(公告)日：2011-10-27
申请号：US13139789
申请日：2009-12-11
申请人： Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Kazuki Ota , Takashi Inoue , Hironobu Miyamoto , Kazuomi Endo
发明人： Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Kazuki Ota , Takashi Inoue , Hironobu Miyamoto , Kazuomi Endo
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/402 , H01L29/0619 , H01L29/2003 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/7787
摘要： There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.
摘要翻译：提供了能够实现反向阻挡特性和低导通电阻的半导体装置。半导体装置包括：第一半导体层，包括沟道层，形成在第一半导体层上的源电极，在第一半导体层上与源极间隔一定距离处形成的漏电极，以及形成在源电极和第一半导体层上的漏电极。漏电极包括第一漏极区，其中第一半导体层和第一漏极区之间的反向电流被阻挡，以及形成在比栅极电极比第一漏极区更远的距离处的第二漏区，半导体层和第二漏极区域比第一半导体层和第一漏极区域之间的电阻低。

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