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71. 发明授权

US06734056B2 Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell 失效
标题翻译： 6F2旋转混合DRAM单元的自对准穿通停止
公开(公告)号：US06734056B2
公开(公告)日：2004-05-11
申请号：US10341831
申请日：2003-01-14
申请人： Jack A. Mandelman , Dureseti Chidambarrao
发明人： Jack A. Mandelman , Dureseti Chidambarrao
IPC分类号： H01L218238
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876 , H01L27/10885 , H01L27/10891
摘要： A 6F2 memory cell structure and a method of fabricating the same. The memory cell structure includes a plurality of memory cells located in a Si-containing substrate which are arranged in rows and columns. Each memory cell includes a double-gated vertical MOSFET having exposed gate conductor regions and two gates formed on opposing sidewalls of the MOSFETs. The memory cell structure also includes a plurality of wordlines overlaying the double-gated vertical MOSFETs and in contact with the exposed gate conductor regions, and a plurality of bitlines that are orthogonal to the wordlines. Trench isolation regions are located adjacent to the rows of memory cells. The memory cell structure also includes a plurality of punch through stop regions located in the Si-containing substrate and self-aligned to the wordlines and bitlines. A portion of the punch through stop regions overlap each other under the bitlines and each region serves to electrically isolate adjacent buried-strap regions from each other.
摘要翻译： 6F 2存储单元结构及其制造方法。存储单元结构包括位于含Si衬底中的以行和列排列的多个存储单元。每个存储单元包括具有暴露的栅极导体区域和形成在MOSFET的相对侧壁上的两个栅极的双门控垂直MOSFET。存储单元结构还包括覆盖双门控垂直MOSFET并与暴露的栅极导体区域接触的多个字线以及与字线正交的多个位线。沟槽隔离区位于与存储单元行相邻的位置。存储单元结构还包括位于含硅衬底中并与字线和位线自对准的多个穿通停止区域。穿通停止区域的一部分在位线之下彼此重叠，并且每个区域用于将相邻的掩埋区域彼此电隔离。

72. 发明授权

US06707095B1 Structure and method for improved vertical MOSFET DRAM cell-to-cell isolation 有权
标题翻译：用于改进垂直MOSFET DRAM单元到单元隔离的结构和方法
公开(公告)号：US06707095B1
公开(公告)日：2004-03-16
申请号：US10290400
申请日：2002-11-06
申请人： Dureseti Chidambarrao , Jack A. Mandelman , Carl J. Radens
发明人： Dureseti Chidambarrao , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10867
摘要： A method is provided for forming a vertical transistor memory cell structure with back-to-back FET cells which are formed in a planar semiconductor substrate with a plurality of deep trenches having vertical FET devices and a plurality of capacitors each located in a separate trench that is formed in the semiconductor substrate. Bilateral outdiffusion strap regions are formed extending into a doped semiconductor well region in the substrate. There are confronting pairs of outdiffusion strap regions extending from adjacent deep benches into the doped well region. An isolation diffusion region is formed in the doped well separating the confronting isolation diffusion regions by extending therebetween.
摘要翻译：提供了一种用于形成具有背对背FET单元的垂直晶体管存储单元结构的方法，其形成在具有多个具有垂直FET器件的深沟槽的平面半导体衬底中，并且多个电容器分别位于单独的沟槽中，形成在半导体衬底中。形成延伸到衬底中的掺杂半导体阱区域中的双边扩散带区域。存在从相邻的深长板延伸到掺杂阱区域的面向对的向外扩散带区域。在掺杂阱中形成隔离扩散区，通过在相互隔离扩散区之间延伸来分离相对的隔离扩散区。

73. 发明授权

US06686637B1 Gate structure with independently tailored vertical doping profile 有权
标题翻译：门结构具有独立定制的垂直掺杂特性
公开(公告)号：US06686637B1
公开(公告)日：2004-02-03
申请号：US10301436
申请日：2002-11-21
申请人： Omer Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl Radens
发明人： Omer Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl Radens
IPC分类号： H01L2978
CPC分类号： H01L29/66545 , H01L21/26586 , H01L21/28035 , H01L21/28044 , H01L29/1083 , H01L29/4925 , H01L29/665
摘要： A gate structure for a semiconductor transistor is disclosed. In an exemplary embodiment, the gate structure includes a lower polysilicon region doped at a first dopant concentration and an upper polysilicon region doped at a second concentration, with the second concentration being different than the first concentration. A conductive barrier layer is disposed between the lower and the upper polysilicon regions, wherein the conductive barrier layer prevents diffusion of impurities between the lower and the upper polysilicon regions.
摘要翻译：公开了一种用于半导体晶体管的栅极结构。在示例性实施例中，栅极结构包括以第一掺杂剂浓度掺杂的下多晶硅区域和以第二浓度掺杂的上多晶硅区域，其中第二浓度不同于第一浓度。导电阻挡层设置在下部和上部多晶硅区域之间，其中导电阻挡层防止杂质在下部和上部多晶硅区域之间的扩散。

74. 发明授权

US06646949B1 Word line driver for dynamic random access memories 有权
标题翻译：用于动态随机存取存储器的字线驱动
公开(公告)号：US06646949B1
公开(公告)日：2003-11-11
申请号：US09537498
申请日：2000-03-29
申请人： Wayne F. Ellis , Louis L-C. Hsu , Jack A. Mandelman , William R. Tonti
发明人： Wayne F. Ellis , Louis L-C. Hsu , Jack A. Mandelman , William R. Tonti
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line for a row of memory elements of a dynamic random access memory. A first transistor is connected to a source of negative potential and to the word line for switching the word line to a source of negative potential in response to a decoder signal. A diode is additionally connected to the word line and to a selector signal. A second transistor applies a positive potential to the word line in response to a decoder signal. The word line is charged to a positive potential. The word line is reset to a substantially negative potential in two stages. In the first stage, conduction is through the diode to a ground connection which dissipates a majority of the charge of the word line. The remaining charge is dissipated during a second stage when the first transistor discharges the word line remaining charge through a source of negative potential.
摘要翻译：用于动态随机存取存储器的一行存储元件的字线。第一晶体管连接到负电位源和字线，用于响应于解码器信号将字线切换到负电位源。二极管另外连接到字线和选择器信号。第二晶体管响应于解码器信号向字线施加正电位。字线被充电到正电位。字线在两个阶段重置为基本上为负的电位。在第一阶段，传导通过二极管到接地连接，消耗字线的大部分电荷。当第一晶体管通过负电位源将字线剩余电荷放电时，剩余电荷在第二阶段消散。

75. 发明授权

US06635525B1 Method of making backside buried strap for SOI DRAM trench capacitor 失效
标题翻译：制造SOI DRAM沟槽电容器的背面掩埋带的方法
公开(公告)号：US06635525B1
公开(公告)日：2003-10-21
申请号：US10161960
申请日：2002-06-03
申请人： Jack A. Mandelman , Herbert L. Ho
发明人： Jack A. Mandelman , Herbert L. Ho
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L21/84 , H01L27/10829 , H01L27/1203 , H01L29/66181
摘要： In SOI integrated circuits having trench capacitor DRAM arrays, the decreasing thickness of the insulating layer causes cross-talk between the passing wordline traveling over the trench capacitor. Increasing the depth of the recess at the top of the trench and undercutting the insulating layer laterally permits the buried strap from the capacitor center electrode to make contact to the back side of the SOI layer, thereby increasing the vertical separation between the passing wordline and the strap.
摘要翻译：在具有沟槽电容器DRAM阵列的SOI集成电路中，绝缘层的减小的厚度导致在沟槽电容器之间传播的通过字线之间的串扰。在沟槽顶部增加凹槽的深度并横向遮蔽绝缘层允许来自电容器中心电极的掩埋带与SOI层的背面接触，从而增加了通过字线和背带。

76. 发明授权

US06630379B2 Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch 失效
标题翻译：制造具有垂直MOSFET和3F位线间距的6F2沟槽电容器DRAM单元的方法
公开(公告)号：US06630379B2
公开(公告)日：2003-10-07
申请号：US10011556
申请日：2001-11-06
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.
摘要翻译：一种存储单元结构，包括平面半导体衬底。深沟槽位于半导体衬底中。深沟槽具有多个侧壁和底部。存储电容器位于深沟槽的底部。垂直晶体管向下延伸存储电容器上方的深沟槽的至少一个侧壁。晶体管具有在邻近深沟槽的衬底的平面中延伸的源极扩散。隔离层向下延伸与垂直晶体管相对的深沟槽的至少另一侧壁。浅沟槽隔离区沿垂直晶体管延伸的横向于侧壁的方向沿着衬底的表面延伸。栅极导体在深沟槽内延伸。一条字线延伸穿过深沟槽并连接到栅极导体。位线延伸在衬底的表面平面之上，并且具有与浅沟槽隔离区之间的源极扩散的接触。

77. 发明授权

US06617702B2 Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate 有权
标题翻译：半导体器件利用对准标记来全面对准半导体衬底的正面和背面
公开(公告)号：US06617702B2
公开(公告)日：2003-09-09
申请号：US09769080
申请日：2001-01-25
申请人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , Tsorng-Dih Yuan
发明人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , Tsorng-Dih Yuan
IPC分类号： H01L23544
CPC分类号： H01L23/48 , H01L21/8221 , H01L23/544 , H01L24/48 , H01L24/73 , H01L27/0694 , H01L2223/54473 , H01L2224/05599 , H01L2224/16225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2224/85399 , H01L2924/00014 , H01L2924/01039 , H01L2924/01077 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , Y10T29/49133 , Y10T29/49155 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one or more substrates. In one embodiment, two circuit systems situated on opposite sides of a substrate are aligned to provide for wireless communications between the two circuit systems through the substrate. In another embodiment, communication devices situated on one or more substrates are aligned to provide for wireless communications between the communication devices through the one or more substrates. In another embodiment, two chips situated on opposite sides of a transparent substrate are aligned to provide for wireless communications between the two chips through the transparent substrate.
摘要翻译：本发明提供了在一个或多个基板的正面和背面上制造或结合到其上的微电子电路系统，例如通信设备和芯片，以提供通过一个或多个基板的电路系统之间的无线通信。在一个实施例中，位于衬底的相对侧上的两个电路系统被对准以提供通过衬底的两个电路系统之间的无线通信。在另一个实施例中，位于一个或多个基板上的通信设备被对准以通过一个或多个基板来提供通信设备之间的无线通信。在另一个实施例中，位于透明基板的相对侧上的两个芯片被对准以提供通过透明基板的两个芯片之间的无线通信。

78. 发明授权

US06573561B1 Vertical MOSFET with asymmetrically graded channel doping 失效
标题翻译：具有不对称梯度通道掺杂的垂直MOSFET
公开(公告)号：US06573561B1
公开(公告)日：2003-06-03
申请号：US10096192
申请日：2002-03-11
申请人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Kevin McStay
发明人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Kevin McStay
IPC分类号： H01L2976
CPC分类号： H01L27/10864 , H01L27/10876 , H01L29/1041 , H01L29/7827
摘要： Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold implant moved from the conventional location of midway between source and drain to a point no more than one third of the channel length below the bottom of the source.
摘要翻译：垂直MOSFET晶体管中的短沟道效应显着降低，在具有垂直非对称阈值注入的晶体管中，DRAM单元中的结漏电减少，其它器件参数不受影响。优选实施例具有将阈值注入的峰值从源极和漏极之间的中途的常规位置移动到不超过源极底部的沟道长度的三分之一的点。

79. 发明授权

US06573137B1 Single sided buried strap 有权
标题翻译：单面埋地带
公开(公告)号：US06573137B1
公开(公告)日：2003-06-03
申请号：US09603442
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
IPC分类号： H01L218242
CPC分类号： H01L27/10864
摘要： A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conductor of the storage capacitor. A layer of silicon is deposited over the barrier material. Dopant ions are implanted at an angle into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.
摘要翻译：一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离环的方法，同时将隔离套环留在深沟槽的其它表面。屏蔽材料沉积在存储电容器的节点导体上方。一层硅沉积在阻挡材料上。掺杂离子以一定角度注入到深沟槽内沉积的硅层中，从而留下沉积的硅沿着深沟槽的一侧被植入。未投影的硅被蚀刻。隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

80. 发明授权

US06544874B2 Method for forming junction on insulator (JOI) structure 失效
标题翻译：用于形成绝缘体结（JOI）结构的方法
公开(公告)号：US06544874B2
公开(公告)日：2003-04-08
申请号：US09928759
申请日：2001-08-13
申请人： Jack A. Mandelman , Kevin K. Chan , Bomy A. Chen , Oleg Gluschenkov , Rajarao Jammy , Victor Ku , Chung H. Lam , Nivo Rovedo
发明人： Jack A. Mandelman , Kevin K. Chan , Bomy A. Chen , Oleg Gluschenkov , Rajarao Jammy , Victor Ku , Chung H. Lam , Nivo Rovedo
IPC分类号： H01L213205
CPC分类号： H01L21/823481 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.
摘要翻译：提供了一种形成JOI结构的方法，该方法允许减少源极/漏极结漏电流和电容。在本发明的方法中，在源极/漏极区域之下形成绝缘体层，但不在沟道区域下方。在本发明中，在形成栅极叠层区域并使包围栅极堆叠区域的半导体表面凹陷之后形成绝缘体层，随后沉积诸如多晶硅的导电材料，以及任选的沉积源极/漏极扩散形成。

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