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71. 发明授权

US06449204B1 DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING DATA STORAGE FROM A ONE BIT/ONE CELL SCHEME IN A NORMAL MODE TO A ONE BIT/TWO CELL SCHEME IN A TWIN-CELL MODE FOR LENGTHENING A REFRESH INTERVAL 失效
标题翻译：动态半导体存储器件，能够将数据存储从正常模式的单位/单个电池方案重新分配到双电池模式中的一个/两个电池模式，以增加刷新间隔
公开(公告)号：US06449204B1
公开(公告)日：2002-09-10
申请号：US09817177
申请日：2001-03-27
申请人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
发明人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
IPC分类号： G11C720
CPC分类号： G11C29/006 , G11C7/1045 , G11C11/401 , G11C11/406 , G11C11/4087 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C29/83 , G11C2029/1204 , G11C2207/104 , G11C2211/4013 , G11C2211/5641
摘要： In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.
摘要翻译：在数据保持模式下，在正常操作模式下的一位/一个单元方案中的数据存储以双位模式重新排列成数据存储，其中数据以一位/双位单元方式存储。在双电池模式中，两个子字线同时被驱动到选择状态，并且在一对位线上读出存储器单元的存储数据，以执行感测操作。因此，可以增加读出电压以改善用于延长刷新间隔的数据保持特性，导致数据保持模式中的功耗降低。

72. 发明授权

US06215720B1 High speed operable semiconductor memory device with memory blocks arranged about the center 失效
标题翻译：具有围绕中心布置的存储块的高速可操作半导体存储器件
公开(公告)号：US06215720B1
公开(公告)日：2001-04-10
申请号：US09478528
申请日：2000-01-06
申请人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
发明人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C5/025 , G11C7/22 , G11C8/12
摘要： A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.
摘要翻译：主控制电路通过四个本地控制电路提供对对应存储器块的访问。存储块被布置成围绕主控制电路和本地控制电路。控制信号到每个存储器块的延迟量被设置为基本上等于抑制控制信号中的偏斜。可以实现高速DRAM。

73. 发明授权

US6072743A High speed operable semiconductor memory device with memory blocks arranged about the center 失效
标题翻译：具有围绕中心布置的存储块的高速可操作半导体存储器件
公开(公告)号：US6072743A
公开(公告)日：2000-06-06
申请号：US110688
申请日：1998-07-07
申请人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
发明人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
IPC分类号： G11C5/02 , G11C7/22 , G11C8/12 , G11C8/00
CPC分类号： G11C7/222 , G11C5/025 , G11C7/22 , G11C8/12
摘要： A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.
摘要翻译：主控制电路通过四个本地控制电路提供对对应存储器块的访问。存储块被布置成围绕主控制电路和本地控制电路。将控制信号到每个存储块的延迟量设置为基本上等于抑制控制信号中的偏移。可以实现高速DRAM。

74. 发明授权

US6064621A Multi-bank clock synchronous type semiconductor memory device having improved memory array and power supply arrangement 失效
标题翻译：具有改进的存储器阵列和电源配置的多存储体时钟同步型半导体存储器件
公开(公告)号：US6064621A
公开(公告)日：2000-05-16
申请号：US113147
申请日：1998-07-10
申请人： Tetsushi Tanizaki , Mitsuya Kinoshita , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Mako Kobayashi
发明人： Tetsushi Tanizaki , Mitsuya Kinoshita , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Mako Kobayashi
IPC分类号： G11C11/41 , G11C5/02 , G11C5/14 , G11C8/00 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/025 , G11C5/14 , G11C8/12
摘要： A rectangular semiconductor substrate region is divided into regions arranged in a plurality of rows and columns, and memory array blocks are provided to surround a central region. The plurality of memory array blocks are divided into a plurality of banks. Peripheral regions on both sides of the rectangular semiconductor substrate region are used as regions for providing sense amplifier power supply circuits, and circuits for generating a voltage to be transmitted onto word lines are provided at the four corner regions of the central region. Thus, a large storage capacity semiconductor memory device operating stably at a high speed and with reduced power consumption can be implemented.
摘要翻译：矩形半导体衬底区域被分成多个行和列布置的区域，并且存储器阵列块被设置为围绕中心区域。多个存储器阵列块被分成多个存储体。矩形半导体衬底区域的两侧的周边区域被用作提供感测放大器电源电路的区域，并且在中心区域的四个角区域处设置用于产生要传输到字线上的电压的电路。因此，可以实现以高速和低功耗稳定运行的大容量半导体存储器件。

75. 发明授权

US5532872A Viewing tube for microscope 失效
标题翻译：观察显微镜管
公开(公告)号：US5532872A
公开(公告)日：1996-07-02
申请号：US274389
申请日：1994-07-13
申请人： Shinobu Sakamoto , Takeshi Fujino
发明人： Shinobu Sakamoto , Takeshi Fujino
IPC分类号： G02B21/00 , G02B7/24 , G02B21/24 , G02B23/00
CPC分类号： G02B21/24 , G02B7/24
摘要： A viewing tube for a microscope has an optical deflecting element such as a mirror for deflecting light from an objective, a supporting member for supporting the optical deflecting element and an eyepiece portion into which the light deflected by the optical deflecting element enters. The supporting member is rotatable around a first shaft and the eyepiece portion is rotatable around a second shaft. An engaging member is mounted on the eyepiece portion in a position whose distance from the second shaft is equal to the distance between the first shaft and the second shaft. Guiding members are provided on the supporting member for engaging with the engaging member and restricting the engaging member in the circumferential direction around the first shaft, so that the supporting member and the optical deflecting element are rotated around the first shaft in accordance with rotation of the eyepiece portion around the second shaft.
摘要翻译：用于显微镜的观察管具有光学偏转元件，例如用于偏转物镜的光的反射镜，用于支撑光学偏转元件的支撑构件和由光学偏转元件偏转的光进入的目镜部分。支撑构件可围绕第一轴旋转，并且目镜部分可围绕第二轴旋转。接合构件在与第二轴的距离等于第一轴和第二轴之间的距离的位置安装在目镜部分上。引导构件设置在支撑构件上，用于与接合构件接合并围绕第一轴限制接合构件沿圆周方向，使得支撑构件和光学偏转构件根据第一轴的旋转围绕第一轴旋转目镜部分围绕第二轴。

76. 发明授权

US5266424A Method of forming pattern and method of manufacturing photomask using such method 失效
标题翻译：使用这种方法形成图案的方法和制造光掩模的方法
公开(公告)号：US5266424A
公开(公告)日：1993-11-30
申请号：US849602
申请日：1992-03-12
申请人： Takeshi Fujino , Yaichiro Watakabe
发明人： Takeshi Fujino , Yaichiro Watakabe
IPC分类号： G03F1/76 , G03F1/78 , G03F7/004 , G03F7/039 , G03F7/26 , G03F7/36 , G03F7/38 , H01L21/027 , H01L21/30 , G03F9/00
CPC分类号： G03F7/36 , G03F7/039 , G03F7/265
摘要： The present invention is mainly directed to provision of a method of producing a highly precise resist pattern, even when a high energy beam is used. Resist containing a base resin including a hydroxyl group, an acid generating agent irradiated with radiation for generating sulfonic acid, and a cross linking agent reacting with the hydroxyl group of the base resin by the catalytic action of the proton of the sulfonic acid thereby cross linking said base resin is applied onto a substrate. The resist is irradiated selectively with radiation, whereby the resist is divided into the exposed part and the non exposed part and the sulfonic acid is generated in the resist of the exposed part. The resist is heated to a first temperature so as to cross link the irradiated part of the resist. The resist is heated to a second temperature and exposed in an atmosphere of a silylating agent, and the surface of the exposed part of the resist is silylated. The resist is dry-developed with oxygen plasma.
摘要翻译：本发明主要涉及提供一种制造高精度抗蚀剂图案的方法，即使使用高能量束也是如此。含有羟基的基础树脂，用辐射产生磺酸的酸产生剂的抗蚀剂和通过磺酸的质子的催化作用与基础树脂的羟基反应的交联剂进行交联所述基础树脂施加到基底上。用辐射选择性地照射抗蚀剂，由此将抗蚀剂分成暴露部分和非暴露部分，并且在暴露部分的抗蚀剂中产生磺酸。将抗蚀剂加热至第一温度，以使抗蚀剂的照射部分交联。将抗蚀剂加热至第二温度并在甲硅烷基化剂的气氛中暴露，并将抗蚀剂的暴露部分的表面甲硅烷基化。抗氧化剂用氧等离子体干发展。

77. 发明授权

US09229400B2 Image forming apparatus having a power supply common to primary transfer and secondary transfer 有权
标题翻译：图像形成装置具有一次转印和二次转印共同的电源
公开(公告)号：US09229400B2
公开(公告)日：2016-01-05
申请号：US13877440
申请日：2011-09-30
申请人： Yoshikuni Ito , Yasuhiro Horiguchi , Takayuki Tanaka , Kenji Karashima , Satoshi Tsuruya , Shinichi Nishida , Takeshi Fujino
发明人： Yoshikuni Ito , Yasuhiro Horiguchi , Takayuki Tanaka , Kenji Karashima , Satoshi Tsuruya , Shinichi Nishida , Takeshi Fujino
IPC分类号： G03G15/16 , G03G15/00
CPC分类号： G03G15/80 , G03G15/1605 , G03G15/1615 , G03G15/162 , G03G15/5004 , G03G2215/0132 , G03G2215/1661
摘要： An image forming apparatus sequentially transfers toner images formed on a plurality of photosensitive drums onto an intermediate transfer member or a transfer material to form an image. The image forming apparatus includes an intermediate transfer belt provided with electrical conductivity, and a power supply for applying a voltage to a secondary transfer roller to pass a current from the secondary transfer roller to the plurality of photosensitive drums via the intermediate transfer belt, thus primarily transferring the toner images from the plurality of photosensitive drums onto the intermediate transfer belt.
摘要翻译：图像形成装置将形成在多个感光鼓上的调色剂图像顺序地转印到中间转印部件或转印材料上以形成图像。图像形成装置包括具有导电性的中间转印带和用于向二次转印辊施加电压以将电流从二次转印辊通过中间转印带传递到多个感光鼓的电源，因此主要将调色剂图像从多个感光鼓转印到中间转印带上。

78. 发明申请

US20140321891A1 IMAGE FORMING APPARATUS 有权
标题翻译：图像形成装置
公开(公告)号：US20140321891A1
公开(公告)日：2014-10-30
申请号：US13995640
申请日：2011-12-09
申请人： Kenji Karashima , Satoshi Tsuruya , Yoshikuni Ito , Yasuhiro Horiguchi , Takeshi Fujino , Takahiro Kawamoto , Takayuki Tanaka , Osamu Iwasaki , Kazunari Hagiwara
发明人： Kenji Karashima , Satoshi Tsuruya , Yoshikuni Ito , Yasuhiro Horiguchi , Takeshi Fujino , Takahiro Kawamoto , Takayuki Tanaka , Osamu Iwasaki , Kazunari Hagiwara
IPC分类号： G03G15/16
CPC分类号： G03G15/1645 , G03G15/0189 , G03G15/1605 , G03G15/161 , G03G15/162 , G03G15/1675 , G03G15/1685 , G03G2215/0132
摘要： The present invention relates to an image forming apparatus that forms an image by consecutively superposing toner images that have been formed on a plurality of photosensitive drums, on an intermediate transfer member or a transfer medium. The image forming apparatus is made compact and operates at a low cost. Since a current supply member supplies a current in a rotational direction of an intermediate transfer belt, multiple first transfer portions do not need corresponding voltage sources. Even in the case where a charging member supplies a current, the potential of the intermediate transfer belt is maintained at a predetermined potential by a constant-voltage element connected to support rollers.
摘要翻译：本发明涉及一种图像形成装置，其通过连续叠加已经形成在多个感光鼓上的调色剂图像，在中间转印部件或转印介质上形成图像。成像装置紧凑并且成本低。由于电流供给部件在中间转印带的旋转方向上供给电流，所以多个第一转印部不需要对应的电压源。即使在充电部件供给电流的情况下，通过连接到支撑辊的恒定电压元件将中间转印带的电位保持在预定电位。

79. 发明授权

US08861720B2 Tamper-resistant memory integrated circuit and encryption circuit using same 有权
标题翻译：防篡改存储器集成电路和加密电路使用相同
公开(公告)号：US08861720B2
公开(公告)日：2014-10-14
申请号：US13812628
申请日：2010-07-28
申请人： Takeshi Fujino
发明人： Takeshi Fujino
IPC分类号： H04L9/06 , G11C7/12 , H04L9/28 , H04L9/00 , G11C7/24 , G11C8/08 , G06F7/58
CPC分类号： G11C8/08 , G06F7/584 , G11C7/24 , H04L9/003 , H04L9/0618 , H04L2209/127
摘要： An integrated memory circuit applies to an S-box of a cryptographic circuit. The integrated memory circuit includes a row decoder, a column decoder, and a sense amplifier composed of a domino-RSL circuit, wherein data reading and data writing from/to memory cells of a memory cell array are performed via two complementary bit lines, and the transition probability of a signal line is equalized by input of random-number data supplied from a random-number generating circuit using an arbiter circuit.
摘要翻译：集成存储器电路适用于密码电路的S盒。集成存储器电路包括行解码器，列解码器和由多米诺骨牌RSL电路组成的读出放大器，其中通过两条互补位线执行从存储单元阵列的存储单元的数据读取和数据写入，以及通过使用仲裁器电路从随机数产生电路提供的随机数数据的输入来均衡信号线的转移概率。

80. 发明申请

US20070053141A1 Electric double layer capacitor 失效
标题翻译：双电层电容器
公开(公告)号：US20070053141A1
公开(公告)日：2007-03-08
申请号：US11517352
申请日：2006-09-08
申请人： Takeshi Fujino
发明人： Takeshi Fujino
IPC分类号： H01G9/00
CPC分类号： H01G9/058 , H01G9/038 , H01G9/155 , H01G11/62 , Y02E60/13
摘要： An electric double layer capacitor suppresses gas generation by decomposition of the electrolyte solution in the capacitor and has a superior performance maintaining ratio. In the electric double layer capacitor including activated carbon polarized electrodes and nonaqueous electrolyte solution, an antacid agent consisting of alkali metal salt of an organic acid is contained in the capacitor.
摘要翻译：电双层电容器通过电容器中的电解质溶液的分解来抑制气体产生，并且具有优异的性能保持率。在包括活性炭极化电极和非水电解质溶液的双电层电容器中，电容器中含有由有机酸的碱金属盐构成的抗酸剂。

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