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1. 发明授权

US5914907A Semiconductor memory device capable of increasing chip yields while maintaining rapid operation 失效
标题翻译：半导体存储器件能够在保持快速操作的同时提高芯片产量
公开(公告)号：US5914907A
公开(公告)日：1999-06-22
申请号：US122760
申请日：1998-07-27
申请人： Mako Kobayashi , Tetsushi Tanizaki , Kazutami Arimoto , Teruhiko Amano , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Mitsuya Kinoshita
发明人： Mako Kobayashi , Tetsushi Tanizaki , Kazutami Arimoto , Teruhiko Amano , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Mitsuya Kinoshita
IPC分类号： G11C29/04 , G11C29/00 , G11C29/42 , G11C8/00 , G11C7/00
CPC分类号： G11C29/80 , G11C29/84
摘要： Regular memory cell arrays are arranged in divided regions in three rows and three columns except for the region located at the second row and the second column. The region located at the intersection of the second row and the second column is provided with a redundant memory cell array. The replacement operation of the regular memory cell arrays with the redundant memory cell array is provided for each memory cell block.
摘要翻译：常规存储单元阵列被布置在除了位于第二行和第二列的区域之外的三行和三列的分割区域中。位于第二行和第二列的交叉点的区域设置有冗余存储单元阵列。为每个存储单元块提供具有冗余存储单元阵列的常规存储单元阵列的替换操作。

2. 发明授权

US06272034B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06272034B1
公开(公告)日：2001-08-07
申请号：US09606402
申请日：2000-06-29
申请人： Mitsuya Kinoshita , Fukashi Morishita , Kazutami Arimoto , Takeshi Fujino , Tetsushi Tanizaki , Takahiro Tsuruda , Teruhiko Amano , Mako Kobayashi
发明人： Mitsuya Kinoshita , Fukashi Morishita , Kazutami Arimoto , Takeshi Fujino , Tetsushi Tanizaki , Takahiro Tsuruda , Teruhiko Amano , Mako Kobayashi
IPC分类号： G11C502
CPC分类号： G11C5/025
摘要： A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.
摘要翻译：控制存储器单元的操作的控制电路部分集中在中心部分，并且热辐射板通过粘合剂放置在其上。具有MPU等的功能的半导体集成电路经由凸块电极放置在控制电路部分上方。控制电路部分和存储块分别形成在分开的芯片上。

3. 发明授权

US06337506B2 Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area 失效
标题翻译：半导体存储器件能够在防止芯片面积增加的同时对噪声进行稳定的操作
公开(公告)号：US06337506B2
公开(公告)日：2002-01-08
申请号：US09116887
申请日：1998-07-16
申请人： Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Takahiro Tsuruda , Mitsuya Kinoshita , Mako Kobayashi
发明人： Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Takahiro Tsuruda , Mitsuya Kinoshita , Mako Kobayashi
IPC分类号： H01L2900
CPC分类号： H01L23/552 , G11C5/14 , H01L21/761 , H01L23/585 , H01L27/0203 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.
摘要翻译：噪声产生源的电源电路和振荡电路等被集中，其周边被保护环包围。提供保护环以至少部分地具有接合焊盘。利用焊盘下方的区域有效地提供保护环，从而在防止芯片面积的增加的同时实现有效的降噪。

4. 发明授权

US06215720B1 High speed operable semiconductor memory device with memory blocks arranged about the center 失效
标题翻译：具有围绕中心布置的存储块的高速可操作半导体存储器件
公开(公告)号：US06215720B1
公开(公告)日：2001-04-10
申请号：US09478528
申请日：2000-01-06
申请人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
发明人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C5/025 , G11C7/22 , G11C8/12
摘要： A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.
摘要翻译：主控制电路通过四个本地控制电路提供对对应存储器块的访问。存储块被布置成围绕主控制电路和本地控制电路。控制信号到每个存储器块的延迟量被设置为基本上等于抑制控制信号中的偏斜。可以实现高速DRAM。

5. 发明授权

US6072743A High speed operable semiconductor memory device with memory blocks arranged about the center 失效
标题翻译：具有围绕中心布置的存储块的高速可操作半导体存储器件
公开(公告)号：US6072743A
公开(公告)日：2000-06-06
申请号：US110688
申请日：1998-07-07
申请人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
发明人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
IPC分类号： G11C5/02 , G11C7/22 , G11C8/12 , G11C8/00
CPC分类号： G11C7/222 , G11C5/025 , G11C7/22 , G11C8/12
摘要： A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.
摘要翻译：主控制电路通过四个本地控制电路提供对对应存储器块的访问。存储块被布置成围绕主控制电路和本地控制电路。将控制信号到每个存储块的延迟量设置为基本上等于抑制控制信号中的偏移。可以实现高速DRAM。

6. 发明授权

US6064621A Multi-bank clock synchronous type semiconductor memory device having improved memory array and power supply arrangement 失效
标题翻译：具有改进的存储器阵列和电源配置的多存储体时钟同步型半导体存储器件
公开(公告)号：US6064621A
公开(公告)日：2000-05-16
申请号：US113147
申请日：1998-07-10
申请人： Tetsushi Tanizaki , Mitsuya Kinoshita , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Mako Kobayashi
发明人： Tetsushi Tanizaki , Mitsuya Kinoshita , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Mako Kobayashi
IPC分类号： G11C11/41 , G11C5/02 , G11C5/14 , G11C8/00 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/025 , G11C5/14 , G11C8/12
摘要： A rectangular semiconductor substrate region is divided into regions arranged in a plurality of rows and columns, and memory array blocks are provided to surround a central region. The plurality of memory array blocks are divided into a plurality of banks. Peripheral regions on both sides of the rectangular semiconductor substrate region are used as regions for providing sense amplifier power supply circuits, and circuits for generating a voltage to be transmitted onto word lines are provided at the four corner regions of the central region. Thus, a large storage capacity semiconductor memory device operating stably at a high speed and with reduced power consumption can be implemented.
摘要翻译：矩形半导体衬底区域被分成多个行和列布置的区域，并且存储器阵列块被设置为围绕中心区域。多个存储器阵列块被分成多个存储体。矩形半导体衬底区域的两侧的周边区域被用作提供感测放大器电源电路的区域，并且在中心区域的四个角区域处设置用于产生要传输到字线上的电压的电路。因此，可以实现以高速和低功耗稳定运行的大容量半导体存储器件。

7. 发明授权

US07139208B2 Refresh-free dynamic semiconductor memory device 失效
公开(公告)号：US07139208B2
公开(公告)日：2006-11-21
申请号：US11165273
申请日：2005-06-24
申请人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
发明人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
IPC分类号： G11C7/20 , G11C5/14
CPC分类号： G11C29/006 , G11C7/1045 , G11C11/401 , G11C11/406 , G11C11/4087 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C29/83 , G11C2029/1204 , G11C2207/104 , G11C2211/4013 , G11C2211/5641
摘要： In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

8. 发明授权

US06507532B1 Semiconductor memory device having row-related circuit operating at high speed 失效
标题翻译：具有行相关电路的半导体存储器件以高速工作
公开(公告)号：US06507532B1
公开(公告)日：2003-01-14
申请号：US09722687
申请日：2000-11-28
申请人： Takeshi Fujino , Kazunari Inoue , Akira Yamazaki , Kazutami Arimoto
发明人： Takeshi Fujino , Kazunari Inoue , Akira Yamazaki , Kazutami Arimoto
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C8/18 , G11C11/4087
摘要： A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.
摘要翻译：中央行相关控制电路与外部时钟信号异步地将内部行地址信号发送到存储器存储体中的每个存储器子块，并且与一个内部时钟信号同步地锁存用于指定存储器子块的块选择信号时钟周期，用于传输到每个存储器子块。备用确定电路与时钟信号异步地执行备用确定。可以提供容易适应银行扩张的半导体存储器件，而不增加芯片面积并且能够实现高速存取。

9. 发明授权

US6151244A Dynamic semiconductor memory device 失效
标题翻译：动态半导体存储器件
公开(公告)号：US6151244A
公开(公告)日：2000-11-21
申请号：US176029
申请日：1998-10-21
申请人： Takeshi Fujino , Kazutami Arimoto
发明人： Takeshi Fujino , Kazutami Arimoto
IPC分类号： H01L21/8247 , G11C11/401 , G11C11/4074 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/24
CPC分类号： G11C11/401 , G11C11/4074
摘要： Memory cell minimum units (MCU) formed of multi-bit one transistor/one capacitor type memory cells are repeatedly arranged in a column direction, and bit line contacts (BCT) are shifted in the column direction relative to a row direction. The bit line contacts are repeatedly shifted with a prescribed number of bit lines as a unit. A set of a read bit line onto which memory cell data are read and a reference bit line supplying a reference potential can be obtained by controlling the voltage of cell plate lines and bit lines for each set of bit lines. Accordingly, a memory cell occupation area can be reduced and sensing operation in the folded bit line arrangement is possible. Consequently, a memory cell occupation area per one bit can be dramatically reduced and sensing operation in the folded bit line arrangement can be performed.
摘要翻译：由多位一晶体管/一电容型存储单元形成的存储单元最小单元（MCU）沿列方向重复排列，并且位线接触（BCT）相对于行方向在列方向上偏移。位线接点以规定数量的位线为单位重复移位。通过控制每组位线的单元板线和位线的电压，可以获得读取存储单元数据的读取位线和提供参考电位的参考位线的集合。因此，可以减小存储器单元占用面积，并且折叠位线布置中的感测操作是可能的。因此，可以显着减少每一位的存储单元占用面积，并且可以执行折叠位线布置中的感测操作。

10. 发明授权

US07102954B2 Semiconductor integrated circuit device having logic circuit and dynamic random access memory on the same chip 有权
标题翻译：具有在同一芯片上的逻辑电路和动态随机存取存储器的半导体集成电路器件
公开(公告)号：US07102954B2
公开(公告)日：2006-09-05
申请号：US10714393
申请日：2003-11-17
申请人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Takeshi Fujino
发明人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Takeshi Fujino
IPC分类号： G11C5/14 , G11C29/06
CPC分类号： H01L27/10897 , G11C5/025 , G11C7/1006 , G11C7/18 , G11C29/12
摘要： In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.
摘要翻译：在存储器电路中，以与逻辑晶体管相同的工艺形成的晶体管用于外围电路，除了要被提供高电压的区域之外。因此，可以简化制造过程，并且提供以高速运行的逻辑合并存储器。

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