专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06385120B1 Power-off state storage apparatus and method 有权
标题翻译：断电状态存储装置和方法
公开(公告)号：US06385120B1
公开(公告)日：2002-05-07
申请号：US09998783
申请日：2001-12-03
申请人： Donald E. Steiss
发明人： Donald E. Steiss
IPC分类号： G11C720
CPC分类号： G11C14/00
摘要： A circuit for power-off state storage in an electronic device having a positive power supply includes a storage circuit comprising first and second storage capacitors and a write circuit having a plurality of N-type transistors coupled to the storage circuit. The write circuit is operable to write a data bit to the first and second storage capacitors. The power-off state storage circuit also has a sense amplifier connected to the storage circuit and that is operable to read the data bit stored by the storage capacitors. The first and second capacitors in the storage circuit are electrically isolated from the positive power supply such that when the positive power supply is terminated any charge stored on the first and second capacitors is prevented from discharging to the terminated power supply.
摘要翻译：一种具有正电源的电子设备中的断电状态存储电路包括：包括第一和第二存储电容器的存储电路和具有耦合到存储电路的多个N型晶体管的写入电路。写入电路可操作以将数据位写入第一和第二存储电容器。断电状态存储电路还具有连接到存储电路的读出放大器，并且可操作以读取由存储电容器存储的数据位。存储电路中的第一和第二电容器与正电源电隔离，使得当正电源终止时，防止存储在第一和第二电容器上的电荷向终端电源放电。

2. 发明授权

US06819618B2 Semiconductor memory device capable of executing refresh operation according to refresh space 失效
公开(公告)号：US06819618B2
公开(公告)日：2004-11-16
申请号：US10697097
申请日：2003-10-31
申请人： Yasuhiro Kashiwazaki
发明人： Yasuhiro Kashiwazaki
IPC分类号： G11C720
CPC分类号： G11C11/40622 , G11C11/406 , G11C11/40615 , G11C2211/4067
摘要： A semiconductor memory device includes a memory having a predetermined number of divided memory spaces, a register that stores data indicating whether a refresh operation is required or not with respect to each memory space, a row address counter that, with reference to the register, counts up an address while skipping an address requiring no refresh operation, to thereby generate an address of the memory space to be refreshed, and a refresh cycle generating circuit that with reference to the register 15, generates a refresh cycle with a cycle which varies according to the number of the memory space requiring the refresh operation.

3. 发明授权

US06335885B1 Semiconductor device having a delay circuit for adjusting the timing of control signals 失效
标题翻译：具有用于调整控制信号的定时的延迟电路的半导体装置
公开(公告)号：US06335885B1
公开(公告)日：2002-01-01
申请号：US09799685
申请日：2001-03-07
申请人： Tadayuki Shimizu
发明人： Tadayuki Shimizu
IPC分类号： G11C720
CPC分类号： G11C8/18 , G11C5/143
摘要： A semiconductor device comprising: a power source voltage detecting member for outputting a voltage detection signal in accordance with a power source voltage; and a delay member which includes an input portion for receiving an input signal, a plurality of delay portions connected to the input portion, a selective portion for selecting one of the delay portions in accordance with the voltage detection signal and an output portion for outputting a delay signal obtained by delaying the input signal by the one of the delay portions.
摘要翻译：一种半导体器件，包括：电源电压检测部件，用于根据电源电压输出电压检测信号; 以及延迟构件，其包括用于接收输入信号的输入部分，连接到输入部分的多个延迟部分，用于根据电压检测信号选择延迟部分之一的选择部分和用于输出延迟信号由延迟部分之一延迟输入信号而获得。

4. 发明授权

US06449204B1 DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING DATA STORAGE FROM A ONE BIT/ONE CELL SCHEME IN A NORMAL MODE TO A ONE BIT/TWO CELL SCHEME IN A TWIN-CELL MODE FOR LENGTHENING A REFRESH INTERVAL 失效
标题翻译：动态半导体存储器件，能够将数据存储从正常模式的单位/单个电池方案重新分配到双电池模式中的一个/两个电池模式，以增加刷新间隔
公开(公告)号：US06449204B1
公开(公告)日：2002-09-10
申请号：US09817177
申请日：2001-03-27
申请人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
发明人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
IPC分类号： G11C720
CPC分类号： G11C29/006 , G11C7/1045 , G11C11/401 , G11C11/406 , G11C11/4087 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C29/83 , G11C2029/1204 , G11C2207/104 , G11C2211/4013 , G11C2211/5641
摘要： In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.
摘要翻译：在数据保持模式下，在正常操作模式下的一位/一个单元方案中的数据存储以双位模式重新排列成数据存储，其中数据以一位/双位单元方式存储。在双电池模式中，两个子字线同时被驱动到选择状态，并且在一对位线上读出存储器单元的存储数据，以执行感测操作。因此，可以增加读出电压以改善用于延长刷新间隔的数据保持特性，导致数据保持模式中的功耗降低。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式