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71. 发明申请

US20070210348A1 Phase-change memory device and methods of fabricating the same 审中-公开
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070210348A1
公开(公告)日：2007-09-13
申请号：US11643702
申请日：2006-12-22
申请人： JongHeui Song , Yong-Sun Ko , Jun Seo , Gyeo-Re Lee , Jae-Seung Hwang
发明人： JongHeui Song , Yong-Sun Ko , Jun Seo , Gyeo-Re Lee , Jae-Seung Hwang
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , G11C2213/52 , H01L27/2436 , H01L45/1233 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/1675
摘要： Example embodiments relate to a phase-change memory device and methods of fabricating the same. A phase-change memory device may include a lower electrode on a semiconductor substrate, a phase-change material layer on the lower electrode, a contact plug between the lower electrode and the phase-change material layer, wherein a first area of the contact plug in contact with a top of the lower electrode is greater than a second area of the contact plug in contact with a bottom of the phase-change material layer and an upper electrode on the phase-change material layer.
摘要翻译：示例实施例涉及相变存储器件及其制造方法。相变存储器件可以包括半导体衬底上的下电极，下电极上的相变材料层，下电极和相变材料层之间的接触插塞，其中接触插塞的第一区域与下电极的顶部接触大于与相变材料层的底部接触的接触插塞的第二区域和相变材料层上的上电极。

72. 发明申请

US20070210334A1 Phase change memory device and method of fabricating the same 审中-公开
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070210334A1
公开(公告)日：2007-09-13
申请号：US11698155
申请日：2007-01-26
申请人： Young-Soo Lim , Yong-Sun Ko , Hyuk-Jin Kwon , Jae-Seung Hwang
发明人： Young-Soo Lim , Yong-Sun Ko , Hyuk-Jin Kwon , Jae-Seung Hwang
IPC分类号： H01L31/00
CPC分类号： H01L45/143 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： Example embodiments relate to a semiconductor memory device and a method of fabricating the same. Other example embodiments relate to a phase change memory device and a method of fabricating the same. There are provided a phase change memory device and a method of fabricating the same for improving or maximizing a production yield. The method comprises: after first removing a first hard mask layer used to form a contact pad electrically connected to a semiconductor substrate, forming a lower electrode to be electrically connected to the contact pad through a first contact hole in a first interlayer insulating layer formed on the contact pad and to have a thickness equal or similar to a thickness of the first interlayer insulating layer; and forming a phase change layer and an upper electrode on the lower electrode. Because change of the resistance value of the lower electrode is reduced or prevented, which has been caused due to a non-uniform thickness of a conventional first hard mask layer, a production yield may be improved.
摘要翻译：示例性实施例涉及半导体存储器件及其制造方法。其他示例性实施例涉及相变存储器件及其制造方法。提供了一种相变存储器件及其制造方法，用于改善或最大化产量。该方法包括：在首先去除用于形成与半导体衬底电连接的接触焊盘的第一硬掩模层之后，通过形成在第一层间绝缘层上的第一层间绝缘层中的第一接触孔形成下电极以与接触焊盘电连接所述接触焊盘的厚度等于或类似于所述第一层间绝缘层的厚度; 并在下电极上形成相变层和上电极。由于由于常规的第一硬掩模层的厚度不均匀而导致的下部电极的电阻值的变化被降低或防止，所以可以提高生产率。

73. 发明申请

US20070194294A1 Phase change memory devices and methods for fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070194294A1
公开(公告)日：2007-08-23
申请号：US11708323
申请日：2007-02-21
申请人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
发明人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
IPC分类号： H01L29/06
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.
摘要翻译：在相变存储器中，在基板上设置层间绝缘层。加热器插头包括设置在穿过层间绝缘层的接触孔中的下部和在层间绝缘层的顶表面上方向上突出的上部。相变图案设置在层间绝缘层上，以覆盖加热器插头的突出部分的顶表面和侧表面。在相变图案和加热器插头的突出部分的侧表面之间插入绝缘间隔件。封盖电极设置在相变图案上。

74. 发明授权

US07205199B2 Method of forming a recess channel trench pattern, and fabricating a recess channel transistor 有权
标题翻译：形成凹槽沟槽图案的方法，以及制造凹槽通道晶体管
公开(公告)号：US07205199B2
公开(公告)日：2007-04-17
申请号：US10917615
申请日：2004-08-13
申请人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
发明人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/823412 , H01L21/823437 , H01L27/10808 , H01L27/10876
摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
摘要翻译：提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。掩模层可以被图案化为曲线型。在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

75. 发明申请

US20070026685A1 Mask structure, method of forming the mask structure, method of forming a pattern using the mask structure and method of forming contacts in a semiconductor device using the mask structure 审中-公开
标题翻译：掩模结构，形成掩模结构的方法，使用掩模结构形成图案的方法以及使用掩模结构在半导体器件中形成接触的方法
公开(公告)号：US20070026685A1
公开(公告)日：2007-02-01
申请号：US11481177
申请日：2006-07-06
申请人： Yong-Kug Bae , Ji-Yong You , Yong-Sun Ko , Seung-Won Seong
发明人： Yong-Kug Bae , Ji-Yong You , Yong-Sun Ko , Seung-Won Seong
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76816
摘要： A mask structure may include a first mask pattern and a second mask pattern formed on an object. When the object includes a first material, the first and the second mask patterns may include a second material and a third material, respectively. The second mask pattern may have at least two openings that expose portions of the object adjacent to sides of the first mask pattern. Because the mask structure has the first and the second mask patterns, desired structures, for example, recesses, trenches, contact holes or patterns may be more precisely formed on or through the object. For example, the first mask pattern may protect the object in an etching process for forming contact holes so that the contact holes may not be connected to each other, for example, when the contact holes have bar shapes or line shapes.
摘要翻译：掩模结构可以包括形成在物体上的第一掩模图案和第二掩模图案。当物体包括第一材料时，第一和第二掩模图案可以分别包括第二材料和第三材料。第二掩模图案可以具有暴露邻近第一掩模图案的侧面的物体的部分的至少两个开口。由于掩模结构具有第一和第二掩模图案，所以可以更精确地形成所需的结构，例如凹槽，沟槽，接触孔或图案。例如，第一掩模图案可以在用于形成接触孔的蚀刻工艺中保护物体，使得接触孔可以不彼此连接，例如当接触孔具有条形或线形时。

76. 发明授权

US07025493B2 Chemical supply system and chemical mixing apparatus 失效
公开(公告)号：US07025493B2
公开(公告)日：2006-04-11
申请号：US10147351
申请日：2002-05-17
申请人： Chung-Ki Min , Yong-Sun Ko , In-Seak Hwang
发明人： Chung-Ki Min , Yong-Sun Ko , In-Seak Hwang
IPC分类号： B01F7/00 , B01F15/02
CPC分类号： B01F7/06 , B01F3/2261 , B01F2215/0096
摘要： A chemical supply system includes at least two supply pipes for supplying at least two different chemicals; a mixing unit connected to the supply pipes for mixing at least two different chemicals to form a chemical mixture, an exhausting unit for exhausing the chemical mixture externally; and a filtering unit provided between the mixing unit and the exhausting unit for filtering the chemical mixture to prevent chemical particles having more than a predetermined size from being exhausted.

77. 发明申请

US20050077568A1 Method of forming a recess channel trench pattern, and fabricating a recess channel transistor 有权
标题翻译：形成凹槽沟槽图案的方法，以及制造凹槽通道晶体管
公开(公告)号：US20050077568A1
公开(公告)日：2005-04-14
申请号：US10917615
申请日：2004-08-13
申请人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
发明人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/423 , H01L29/76 , H01L21/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/823412 , H01L21/823437 , H01L27/10808 , H01L27/10876
摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
摘要翻译：提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。掩模层可以被图案化为曲线型。在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

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