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1. 发明申请

US20070210348A1 Phase-change memory device and methods of fabricating the same 审中-公开
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070210348A1
公开(公告)日：2007-09-13
申请号：US11643702
申请日：2006-12-22
申请人： JongHeui Song , Yong-Sun Ko , Jun Seo , Gyeo-Re Lee , Jae-Seung Hwang
发明人： JongHeui Song , Yong-Sun Ko , Jun Seo , Gyeo-Re Lee , Jae-Seung Hwang
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , G11C2213/52 , H01L27/2436 , H01L45/1233 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/1675
摘要： Example embodiments relate to a phase-change memory device and methods of fabricating the same. A phase-change memory device may include a lower electrode on a semiconductor substrate, a phase-change material layer on the lower electrode, a contact plug between the lower electrode and the phase-change material layer, wherein a first area of the contact plug in contact with a top of the lower electrode is greater than a second area of the contact plug in contact with a bottom of the phase-change material layer and an upper electrode on the phase-change material layer.
摘要翻译：示例实施例涉及相变存储器件及其制造方法。相变存储器件可以包括半导体衬底上的下电极，下电极上的相变材料层，下电极和相变材料层之间的接触插塞，其中接触插塞的第一区域与下电极的顶部接触大于与相变材料层的底部接触的接触插塞的第二区域和相变材料层上的上电极。

2. 发明申请

US20060286298A1 Thin layer structure and method of forming the same 失效
公开(公告)号：US20060286298A1
公开(公告)日：2006-12-21
申请号：US11449839
申请日：2006-06-09
申请人： Jae-Kyu Ha , Jun Seo , Min-Chul Chae , Yong-Sun Ko , Young-Mi Lee , Jae-Seung Hwang
发明人： Jae-Kyu Ha , Jun Seo , Min-Chul Chae , Yong-Sun Ko , Young-Mi Lee , Jae-Seung Hwang
IPC分类号： B05D5/00
CPC分类号： H01L21/84 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/02667 , H01L21/76262 , H01L27/1203
摘要： In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.

3. 发明授权

US07667221B2 Phase change memory devices and methods for fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07667221B2
公开(公告)日：2010-02-23
申请号：US11708323
申请日：2007-02-21
申请人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
发明人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.
摘要翻译：在相变存储器中，在基板上设置层间绝缘层。加热器插头包括设置在穿过层间绝缘层的接触孔中的下部和在层间绝缘层的顶表面上方向上突出的上部。相变图案设置在层间绝缘层上，以覆盖加热器插头的突出部分的顶表面和侧表面。在相变图案和加热器插头的突出部分的侧表面之间插入绝缘间隔件。封盖电极设置在相变图案上。

4. 发明授权

US07534704B2 Thin layer structure and method of forming the same 失效
标题翻译：薄层结构及其形成方法
公开(公告)号：US07534704B2
公开(公告)日：2009-05-19
申请号：US11449839
申请日：2006-06-09
申请人： Jae-Kyu Ha , Jun Seo , Min-Chul Chae , Yong-Sun Ko , Young-Mi Lee , Jae-Seung Hwang
发明人： Jae-Kyu Ha , Jun Seo , Min-Chul Chae , Yong-Sun Ko , Young-Mi Lee , Jae-Seung Hwang
IPC分类号： H01L21/20
CPC分类号： H01L21/84 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/02667 , H01L21/76262 , H01L27/1203
摘要： In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.
摘要翻译：在薄层结构及其形成方法中，在基板上形成第一预备绝缘图案，并且包括暴露基板的第一开口。在第一开口中形成包括单晶硅的一种或多种初步种子图案。在第一预备绝缘图案和一个或多个初步种子图案上形成第二绝缘层。通过蚀刻第一和第二绝缘层和一个或多个初步种子图案来形成第二绝缘图案，第一绝缘图案和一个或多个种子图案。第二绝缘图案包括具有平坦底部的第二开口。在第二开口中形成单晶硅图案，其中单晶硅图案的中心厚度与其周边厚度基本相同，从而减少或防止半导体器件中的变薄缺陷。

5. 发明申请

US20070194294A1 Phase change memory devices and methods for fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070194294A1
公开(公告)日：2007-08-23
申请号：US11708323
申请日：2007-02-21
申请人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
发明人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
IPC分类号： H01L29/06
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.
摘要翻译：在相变存储器中，在基板上设置层间绝缘层。加热器插头包括设置在穿过层间绝缘层的接触孔中的下部和在层间绝缘层的顶表面上方向上突出的上部。相变图案设置在层间绝缘层上，以覆盖加热器插头的突出部分的顶表面和侧表面。在相变图案和加热器插头的突出部分的侧表面之间插入绝缘间隔件。封盖电极设置在相变图案上。

6. 发明授权

US08728882B2 Manufacturing method for thin film transistor array panel 有权
标题翻译：薄膜晶体管阵列面板的制造方法
公开(公告)号：US08728882B2
公开(公告)日：2014-05-20
申请号：US13569586
申请日：2012-08-08
申请人： Jae Seung Hwang , Jae-Won Lee , Jun Seo
发明人： Jae Seung Hwang , Jae-Won Lee , Jun Seo
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/32135 , H01L21/32139 , H01L27/1288
摘要： A manufacturing method for a thin film transistor array panel includes: providing a gate line including a gate electrode, on a substrate; providing a gate insulating layer covering the gate line; providing a semiconductor material layer on the gate insulating layer; providing a data wire material layer on the semiconductor material layer; providing a first photosensitive film pattern on the data wire material layer; etching the data wire material layer by using the first photosensitive film pattern as a mask; providing a second photosensitive film pattern by etching back the first photosensitive film pattern; etching the semiconductor material layer by using the second photosensitive film pattern as a mask; and etching the data wire material layer by using the second photosensitive film pattern as a mask to form a source electrode and a drain electrode. The etching the semiconductor material layer uses a first non-sulfur fluorinated gas.
摘要翻译：薄膜晶体管阵列板的制造方法包括：在基板上设置包括栅电极的栅极线; 提供覆盖所述栅极线的栅极绝缘层; 在栅绝缘层上提供半导体材料层; 在半导体材料层上提供数据线材料层; 在数据线材料层上提供第一感光膜图案; 通过使用第一感光膜图案作为掩模来蚀刻数据线材层; 通过蚀刻第一感光膜图案提供第二感光膜图案; 通过使用第二感光膜图案作为掩模蚀刻半导体材料层; 并通过使用第二感光膜图案作为掩模来蚀刻数据线材层，以形成源电极和漏电极。半导体材料层的蚀刻使用第一非硫氟化气体。

7. 发明授权

US08216944B2 Methods of forming patterns in semiconductor devices 有权
标题翻译：在半导体器件中形成图案的方法
公开(公告)号：US08216944B2
公开(公告)日：2012-07-10
申请号：US12715788
申请日：2010-03-02
申请人： Yong-Hyun Kwon , Jun Seo , Jae-Seung Hwang , Ji-Young Lee
发明人： Yong-Hyun Kwon , Jun Seo , Jae-Seung Hwang , Ji-Young Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088
摘要： Methods of forming patterns in semiconductor devices are provided including forming first patterns spaced apart from one another on an object structure. A first sacrificial layer is formed conformally on the first patterns and the object structure. A second pattern is formed on a sidewall of the first sacrificial layer, the second pattern having a height smaller than that of the first pattern from an upper surface of the object structure. The first patterns are selectively removed to form an opening that exposes the object structure. A third pattern is formed on a sidewall of the opening.
摘要翻译：提供了在半导体器件中形成图案的方法，包括在对象结构上形成彼此间隔开的第一图案。第一牺牲层在第一图案和对象结构上保形地形成。第二图案形成在第一牺牲层的侧壁上，第二图案具有比目标结构的上表面小的第一图案的高度。选择性地去除第一图案以形成露出对象结构的开口。第三图案形成在开口的侧壁上。

8. 发明授权

US07989279B2 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07989279B2
公开(公告)日：2011-08-02
申请号：US12136626
申请日：2008-06-10
申请人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
发明人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
IPC分类号： H01L21/338 , H01L21/336
CPC分类号： H01L23/535 , H01L21/743 , H01L27/105 , H01L27/1052 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.
摘要翻译：提供一种制造半导体器件的方法，其中可以形成具有细间距和均匀厚度的多条导线。该方法包括在绝缘层中形成多个第一导电图案作为闭合曲线，在绝缘层上形成多个掩模图案，掩模图案暴露出每个第一导电图案的端部，并且形成多个第二导电通过去除每个第一导电图案的端部，将绝缘层中的图案作为线。

9. 发明申请

US20100221921A1 Methods of Forming Patterns in Semiconductor Devices 有权
标题翻译：在半导体器件中形成图案的方法
公开(公告)号：US20100221921A1
公开(公告)日：2010-09-02
申请号：US12715788
申请日：2010-03-02
申请人： Yong-Hyun Kwon , Jun Seo , Jae-Seung Hwang , Ji-Young Lee
发明人： Yong-Hyun Kwon , Jun Seo , Jae-Seung Hwang , Ji-Young Lee
IPC分类号： H01L21/3105
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088
摘要： Methods of forming patterns in semiconductor devices are provided including forming first patterns spaced apart from one another on an object structure. A first sacrificial layer is formed conformally on the first patterns and the object structure. A second pattern is formed on a sidewall of the first sacrificial layer, the second pattern having a height smaller than that of the first pattern from an upper surface of the object structure. The first patterns are selectively removed to form an opening that exposes the object structure. A third pattern is formed on a sidewall of the opening.
摘要翻译：提供了在半导体器件中形成图案的方法，包括在对象结构上形成彼此间隔开的第一图案。第一牺牲层在第一图案和对象结构上保形地形成。第二图案形成在第一牺牲层的侧壁上，第二图案具有比目标结构的上表面小的第一图案的高度。选择性地去除第一图案以形成露出对象结构的开口。第三图案形成在开口的侧壁上。

10. 发明授权

US08361849B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08361849B2
公开(公告)日：2013-01-29
申请号：US13183574
申请日：2011-07-15
申请人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
发明人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
IPC分类号： H01L21/338 , H01L21/336
CPC分类号： H01L23/535 , H01L21/743 , H01L27/105 , H01L27/1052 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.
摘要翻译：提供一种制造半导体器件的方法，其中可以形成具有细间距和均匀厚度的多条导线。该方法包括在绝缘层中形成多个第一导电图案作为闭合曲线，在绝缘层上形成多个掩模图案，掩模图案暴露出每个第一导电图案的端部，并且形成多个第二导电通过去除每个第一导电图案的端部，将绝缘层中的图案作为线。

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