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71. 发明申请

US20070278541A1 Spacer engineering on CMOS devices 审中-公开
标题翻译： CMOS器件上的间隔工程
公开(公告)号：US20070278541A1
公开(公告)日：2007-12-06
申请号：US11446912
申请日：2006-06-05
申请人： Chien-Chao Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/1083 , H01L29/6656 , H01L29/7842
摘要： A MOS device having a reduced LDD dopant diffusion length and a method for forming the same are provided. The MOS device includes a gate stack over a semiconductor substrate, a spacer liner on a sidewall of the gate stack and having a portion over the semiconductor substrate, and a spacer over the spacer liner. The spacer for a PMOS device preferably has a tensile stress, and the spacer for an NMOS device preferably has a compressive stress.
摘要翻译：提供具有降低的LDD掺杂剂扩散长度的MOS器件及其形成方法。 MOS器件包括在半导体衬底上的栅极堆叠，在栅极堆叠的侧壁上的间隔衬垫，并且具有半导体衬底上的部分，以及间隔衬垫上的间隔物。用于PMOS器件的间隔物优选具有拉伸应力，并且用于NMOS器件的间隔物优选地具有压应力。

72. 发明申请

US20070228372A1 Method for Fabricating a Body Contact in a Finfet Structure and a Device Including the Same 有权
标题翻译：在Finfet结构中制造身体接触的方法和包括其的设备
公开(公告)号：US20070228372A1
公开(公告)日：2007-10-04
申请号：US11761547
申请日：2007-06-12
申请人： Kuo-Nan Yang , Yi-Lang Chen , Hou-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Kuo-Nan Yang , Yi-Lang Chen , Hou-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L23/58
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78615
摘要： A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator substrate. A source region and a drain region form two ends of a cross bar of the T-shaped active region and a body contact region forms a leg of the T-shaped active region. A gate oxide layer is grown on the active region. A polysilicon layer is deposited overlying the gate oxide layer and patterned to form a gate, where an end of the gate partially overlies the body contact region to complete formation of a Finfet device with body contact.
摘要翻译：提供了一种用于制造具有主体触点的Finfet器件的方法和使用该方法制造的器件。在一个示例中，提供绝缘体上硅衬底。在绝缘体上硅衬底的硅层中限定T形有源区。源极区域和漏极区域形成T形有源区域的横杆的两个端部，并且主体接触区域形成T形有源区域的腿部。在有源区上生长栅氧化层。沉积覆盖栅极氧化物层的多晶硅层并图案化以形成栅极，其中栅极的一端部分覆盖在主体接触区域上，以完成具有身体接触的Finfet器件的形成。

73. 发明申请

US20070222035A1 Stress intermedium engineering 审中-公开
标题翻译：应力中介工程
公开(公告)号：US20070222035A1
公开(公告)日：2007-09-27
申请号：US11387601
申请日：2006-03-23
申请人： Chien-Chao Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L29/06
CPC分类号： H01L29/78 , H01L29/7843 , H01L29/7845
摘要： Embodiments of the invention provide structures and methods for forming a strained MOS transistor. A stressor layer is formed over the transistor. Embodiments include an intermedium layer between the stressor layer and a portion of the transistor. In an embodiment, the intermedium comprises a layer formed between the stressor layer and the gate electrode sidewall spacers. In another embodiment, the intermedium comprises a silicided portion of the substrate formed over the LDS/LDD regions. A transistor that includes the intermedium and, stressor layer has a vertically oriented stress within the channel region. The vertically oriented stress is tensile in a PMOS transistor and compressive in an NMOS transistor.
摘要翻译：本发明的实施例提供了用于形成应变MOS晶体管的结构和方法。在晶体管上方形成应力层。实施例包括应力层与晶体管的一部分之间的中间层。在一个实施例中，中间层包括在应力层和栅电极侧壁间隔件之间形成的层。在另一个实施例中，中间层包括在LDS / LDD区上形成的衬底的硅化物部分。包括中间层和应力层的晶体管在沟道区域内具有垂直取向的应力。垂直取向的应力是PMOS晶体管中的拉伸和NMOS晶体管中的压缩。

74. 发明申请

US20070161195A1 Structure and method for a sidewall SONOS memory device 有权
标题翻译：侧壁SONOS存储器件的结构和方法
公开(公告)号：US20070161195A1
公开(公告)日：2007-07-12
申请号：US11327185
申请日：2006-01-06
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/66833 , H01L29/7923 , Y10S438/954
摘要： A system and method for a sidewall SONOS memory device is provided. An electronic device includes a non-volatile memory. A substrate includes source/drain regions. A gate stack is directly over the substrate and between the source/drain regions. The gate stack has a sidewall. A nitride spacer is formed adjacent to the gate stack. A first oxide material is formed directly adjacent the spacer. An oxide-nitride-oxide structure is formed between the spacer and the gate stack. The oxide-nitride-oxide structure has a generally L-shaped cross-section on at least one side of the gate stack. The oxide-nitride-oxide structure includes a vertical portion and a horizontal portion. The vertical portion is substantially aligned with the sidewall and located between the first oxide material and the gate sidewall. The horizontal portion is substantially aligned with the substrate and located between the first oxide and the substrate.
摘要翻译：提供了一种用于侧壁SONOS存储器件的系统和方法。电子设备包括非易失性存储器。衬底包括源极/漏极区域。栅极堆叠直接在衬底上并且在源极/漏极区域之间。栅极堆叠具有侧壁。在栅叠层附近形成氮化物间隔物。第一氧化物材料直接邻近间隔物形成。在间隔物和栅极叠层之间形成氧化物 - 氧化物 - 氧化物结构。氧化物 - 氧化物 - 氧化物结构在栅极堆叠的至少一侧具有大致L形的横截面。氧化物 - 氮化物 - 氧化物结构包括垂直部分和水平部分。垂直部分基本上与侧壁对准并且位于第一氧化物材料和栅极侧壁之间。水平部分基本上与衬底对准并位于第一氧化物和衬底之间。

75. 发明授权

US07183137B2 Method for dicing semiconductor wafers 有权
标题翻译：切割半导体晶片的方法
公开(公告)号：US07183137B2
公开(公告)日：2007-02-27
申请号：US10725697
申请日：2003-12-01
申请人： Hsin-Hui Lee , Chien-Chao Huang , Chao-Hsiung Wang , Fu-Liang Yang , Chenming Hu
发明人： Hsin-Hui Lee , Chien-Chao Huang , Chao-Hsiung Wang , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/50 , H01L21/78
CPC分类号： H01L21/78 , B28D5/00
摘要： A method is disclosed for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure.
摘要翻译：公开了一种用于切割具有金刚石结构的基底材料的晶片的方法。晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。

76. 发明授权

US07176092B2 Gate electrode for a semiconductor fin device 有权
标题翻译：用于半导体鳍片器件的栅电极
公开(公告)号：US07176092B2
公开(公告)日：2007-02-13
申请号：US10825872
申请日：2004-04-16
申请人： Yee-Chia Yeo , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction and activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.
摘要翻译：用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料，其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。该方法还包括对栅电极材料进行平面化和掺杂，而不掺杂源极/漏极有源区，然后对栅电极材料进行构图。栅极电极材料的平面化可以在引入和激活掺杂剂杂质之前进行，或者可以跟随掺杂剂杂质的引入和激活。在栅电极被图案化之后，掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。

77. 发明申请

US20060202237A1 Metal gate semiconductor device and manufacturing method 有权
标题翻译：金属栅极半导体器件及其制造方法
公开(公告)号：US20060202237A1
公开(公告)日：2006-09-14
申请号：US11400853
申请日：2006-04-10
申请人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
发明人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
IPC分类号： H01L29/768
CPC分类号： H01L29/66553 , H01L21/28097 , H01L21/82345 , H01L21/823468 , H01L29/665 , H01L29/66507 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.
摘要翻译：一种用于制造金属栅极的方法包括提供包括位于基板上的栅电极的基板。形成多个层，包括位于衬底上的第一层和栅电极以及与第一层相邻的第二层。这些层被蚀刻以形成多个相邻的间隔物，包括位于衬底上并且邻近栅电极的第一间隔物和邻近第一间隔物的第二间隔物。然后蚀刻第一间隔物，并且在紧邻栅电极的器件上形成金属层。然后金属层与栅电极反应形成金属栅极。

78. 发明授权

US07105897B2 Semiconductor structure and method for integrating SOI devices and bulk devices 有权
标题翻译：用于集成SOI器件和散装器件的半导体结构和方法
公开(公告)号：US07105897B2
公开(公告)日：2006-09-12
申请号：US10977236
申请日：2004-10-28
申请人： Hao-Yu Chen , Fu-Liang Yang , Hung-Wei Chen , Ping-Kun Wu , Chao-Hsiung Wang
发明人： Hao-Yu Chen , Fu-Liang Yang , Hung-Wei Chen , Ping-Kun Wu , Chao-Hsiung Wang
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/823481 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on the first substrate in the SOI area; and a second substrate, on which the SOI device is formed, stacked on the insulation layer. The surface of the first substrate is not on the substantially same plane as the surface of the second substrate.
摘要翻译：本发明公开了一种用于集成至少一个体器件和至少一个绝缘体上硅（SOI）器件的方法和半导体结构。半导体结构包括具有SOI区域和体积区域的第一基板，在其上形成散装器件; 形成在SOI区域的第一基板上的绝缘层; 以及在其上形成有SOI器件的第二衬底，堆叠在绝缘层上。第一基板的表面不在与第二基板的表面基本相同的平面上。

79. 发明申请

US20060065948A1 Inductor energy loss reduction techniques 有权
标题翻译：电感衰减技术
公开(公告)号：US20060065948A1
公开(公告)日：2006-03-30
申请号：US10950046
申请日：2004-09-24
申请人： Andrew Yeh , Alex Chang , Sung-Pi Tseng , Chang-Yun Chang , Hao-Yu Chen , Fu-Liang Yang
发明人： Andrew Yeh , Alex Chang , Sung-Pi Tseng , Chang-Yun Chang , Hao-Yu Chen , Fu-Liang Yang
IPC分类号： H01L29/00
CPC分类号： H01L27/08 , H01F17/0006 , H01F2017/008 , H01L21/761 , H01L21/762 , H01L27/0688
摘要： An inductive device including an inductor coil located over a substrate, at least one electrically insulating layer interposing the inductor coil and the substrate, and a plurality of current interrupters each extending into the substrate, wherein a first aggregate outer boundary of the plurality of current interrupters substantially encompasses a second aggregate outer boundary of the inductor coil.
摘要翻译：一种电感器件，包括位于衬底上的电感器线圈，插入电感线圈和衬底的至少一个电绝缘层和各自延伸到衬底中的多个电流中断器，其中多个电流断流器的第一聚集外边界基本上包含电感线圈的第二聚集外边界。

80. 发明授权

US06979867B2 SOI chip with mesa isolation and recess resistant regions 有权
公开(公告)号：US06979867B2
公开(公告)日：2005-12-27
申请号：US11022730
申请日：2004-12-27
申请人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L23/58
CPC分类号： H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.

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