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1. 发明授权

US09006826B2 Butted contact shape to improve SRAM leakage current 有权
标题翻译：对接接触形状，提高SRAM漏电流
公开(公告)号：US09006826B2
公开(公告)日：2015-04-14
申请号：US13470496
申请日：2012-05-14
申请人： Tzyh-Cheang Lee
发明人： Tzyh-Cheang Lee
IPC分类号： H01L21/8244 , H01L21/768 , H01L23/485 , H01L27/11
CPC分类号： H01L27/1104 , H01L21/76802 , H01L21/76816 , H01L21/76877 , H01L21/76895 , H01L23/485 , H01L2924/00 , H01L2924/0002 , Y10S257/902 , Y10S257/903 , Y10S257/904
摘要： The present disclosure relates to an SRAM memory cell. The SRAM memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area. A butted contact extends along a length (i.e., the larger dimension of the butted contact) from a position above the active area to a position above the gate region. The butted contact contains a plurality of distinct regions having different widths (i.e., the smaller dimensions of the butted contact), such that a region spanning the active area and gate region has width less than the regions in contact with the active area or gate region. By making the width of the region spanning the active area and gate region smaller than the regions in contact with the active area or gate, the etch rate is reduced at a junction of the gate region with the active area, thereby preventing etch back of the gate material and leakage current.
摘要翻译：本公开涉及SRAM存储单元。 SRAM存储单元具有半导体衬底，其具有有源区和位于有源区上方的栅极区。对接触头沿着有效区域上方的位置的长度（即，对接触点的较大尺寸）延伸到栅极区域上方的位置。对接触点包含具有不同宽度的多个不同区域（即，对接触点的较小尺寸），使得横跨有源区域和栅极区域的区域的宽度小于与有源区域或栅极区域接触的区域。通过使跨越有源区域和栅极区域的区域的宽度小于与有源区域或栅极接触的区域，在栅极区域与有源区域的接合处蚀刻速率降低，从而防止蚀刻栅极材料和漏电流。

2. 发明授权

US08618524B2 Phase change memory with various grain sizes 有权
标题翻译：具有各种晶粒尺寸的相变记忆体
公开(公告)号：US08618524B2
公开(公告)日：2013-12-31
申请号：US13029436
申请日：2011-02-17
申请人： Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
发明人： Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
IPC分类号： H01L45/00
CPC分类号： H01L45/12 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1683
摘要： A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.
摘要翻译：存储器件包括相变元件，该相变元件还包括具有第一晶粒尺寸的第一相变层; 以及在所述第一相变层上的第二相变层。第一和第二相变层是相变元件的深度区域。第二相变层具有与第一平均晶粒尺寸不同的第二平均晶粒尺寸。

3. 发明授权

US08154003B2 Resistive non-volatile memory device 有权
标题翻译：电阻式非易失性存储器件
公开(公告)号：US08154003B2
公开(公告)日：2012-04-10
申请号：US11836593
申请日：2007-08-09
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Tseung-Yuen Tseng , Chih-Yang Lin
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Tseung-Yuen Tseng , Chih-Yang Lin
IPC分类号： H01L45/00
CPC分类号： H01L45/12 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1608
摘要： The present disclosure provides a memory cell. The memory cell includes a first electrode, a variable resistive material layer coupled to the first electrode, a metal oxide layer coupled the variable resistive material layer; and a second electrode coupled to the metal oxide layer. In an embodiment, the metal oxide layer provides a constant resistance.
摘要翻译：本公开提供了一种存储单元。存储单元包括第一电极，耦合到第一电极的可变电阻材料层，耦合可变电阻材料层的金属氧化物层; 以及耦合到所述金属氧化物层的第二电极。在一个实施例中，金属氧化物层提供恒定的电阻。

4. 发明申请

US20100140580A1 Phase Change Memory 有权
标题翻译：相变记忆
公开(公告)号：US20100140580A1
公开(公告)日：2010-06-10
申请号：US12703571
申请日：2010-02-10
申请人： Tzyh-Cheang Lee , Ming-Yi Yang , Fu-Liang Yang , Denny Duan-lee Tang
发明人： Tzyh-Cheang Lee , Ming-Yi Yang , Fu-Liang Yang , Denny Duan-lee Tang
IPC分类号： H01L45/00
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material.
摘要翻译：提供了相变存储器。该方法包括在第一电介质层中形成接触塞。形成第二电介质层，覆盖第一电介质层和形成在其中的沟槽，暴露接触插塞的部分。在沟槽的表面上形成金属层。从金属层形成一个或多个加热器，使得每个加热器沿着沟槽的一个或多个侧壁形成，其中加热器沿侧壁的部分不包括相邻侧壁的拐角区域。沟槽填充有第三电介质层，并且在第三介电层上形成第四电介质层。在第四电介质层中形成沟槽并填充相变材料。在相变材料上形成电极。

5. 发明授权

US07482231B2 Manufacturing of memory array and periphery 有权
标题翻译：内存阵列和周边的制造
公开(公告)号：US07482231B2
公开(公告)日：2009-01-27
申请号：US11529067
申请日：2006-09-28
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L21/8239
CPC分类号： H01L29/4983 , H01L21/28282 , H01L21/823828 , H01L21/823864 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： Method of manufacturing a semiconductor chip. An array region gate stack is formed on an array region of a substrate and a periphery region gate stack is formed on a periphery region of a substrate. A first dielectric material, a charge-storing material, and a second dielectric material are deposited over the substrate. Portions of the first dielectric material, the charge-storing material, and the second dielectric material are removed to form storage structures on the array region gate stack and on the periphery region gate stack. The storage structures have a generally L-shaped cross-section. A first source/drain region is formed in the array region well. A third dielectric material and a spacer material are deposited over the substrate. Portions of the third dielectric material and the spacer material are removed to form spacers. A second source/drain region is formed in the periphery region well.
摘要翻译：制造半导体芯片的方法在基板的阵列区域上形成阵列区域栅极叠层，并且在基板的周边区域上形成周边区域栅叠层。在衬底上沉积第一介电材料，电荷存储材料和第二介电材料。去除第一介电材料的部分，电荷存储材料和第二介电材料，以在阵列区域栅极叠层和周边区域栅叠层上形成存储结构。存储结构具有大致L形的横截面。在阵列区域中形成第一源极/漏极区域。在衬底上沉积第三介电材料和间隔物材料。去除第三电介质材料和间隔物材料的部分以形成间隔物。在周边区域中形成第二源极/漏极区域。

6. 发明申请

US20080285328A1 Phase Change Memory 失效
标题翻译：相变记忆
公开(公告)号：US20080285328A1
公开(公告)日：2008-11-20
申请号：US11749017
申请日：2007-05-15
申请人： Tzyh-Cheang Lee , Ming-Yi Yang , Fu-Liang Yang , Denny Duan-lee Tang
发明人： Tzyh-Cheang Lee , Ming-Yi Yang , Fu-Liang Yang , Denny Duan-lee Tang
IPC分类号： G11C11/56 , H01L45/00
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls and a portion of the bottom of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material.
摘要翻译：提供了相变存储器。该方法包括在第一电介质层中形成接触塞。形成第二电介质层，覆盖第一电介质层和形成在其中的沟槽，暴露接触插塞的部分。在沟槽的表面上形成金属层。从金属层形成一个或多个加热器，使得每个加热器沿沟槽的一个或多个侧壁和底部的一部分形成，其中加热器沿着侧壁的部分不包括相邻侧壁的拐角区域。沟槽填充有第三电介质层，并且在第三介电层上形成第四电介质层。在第四电介质层中形成沟槽并填充相变材料。在相变材料上形成电极。

7. 发明申请

US20070075385A1 Sidewall SONOS gate structure with dual-thickness oxide and method of fabricating the same 审中-公开
标题翻译：侧壁SONOS门结构与双层氧化物及其制造方法相同
公开(公告)号：US20070075385A1
公开(公告)日：2007-04-05
申请号：US11243165
申请日：2005-10-04
申请人： Tzyh-Cheang Lee , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/7923 , H01L29/40117 , H01L29/4234
摘要： A SONOS gate structure has an oxide structure on a substrate having gate pattern thereon. The oxide structure has a relatively thinner oxide portion on the substrate for keeping good program/erase efficiency, and a relatively thicker oxide portion on sidewalls of the gate pattern for inhibiting gate disturb. Trapping dielectric spacers are on formed the oxide structure laterally adjacent to said sidewalls of said gate pattern respectively.
摘要翻译： SONOS栅极结构在其上具有栅极图案的衬底上具有氧化物结构。氧化物结构在衬底上具有相对较薄的氧化物部分，用于保持良好的编程/擦除效率，并且在用于抑制栅极干扰的栅极图案的侧壁上的相对较厚的氧化物部分。捕获电介质间隔物分别形成在与所述栅极图案的所述侧壁相邻的氧化物结构上。

8. 发明申请

US20050186735A1 Method for fabricating memory device 有权
标题翻译：制造存储器件的方法
公开(公告)号：US20050186735A1
公开(公告)日：2005-08-25
申请号：US10788194
申请日：2004-02-25
申请人： Tzyh-Cheang Lee
发明人： Tzyh-Cheang Lee
IPC分类号： H01L21/28 , H01L21/336 , H01L21/762 , H01L21/8238 , H01L27/115
CPC分类号： H01L21/28273 , H01L21/76224 , H01L27/115
摘要： The present invention relates to a method for fabricating a memory device. According to this invention, because the trenches for the isolation structures are etched simultaneously as patterning the first conductive layer and the first dielectric layer, the formed isolation structures are self-aligned with the stacked gate structures, thus increasing the reliability for the memory device by avoiding misalignment problems.
摘要翻译：本发明涉及一种用于制造存储器件的方法。根据本发明，由于在图案化第一导电层和第一介电层的同时蚀刻用于隔离结构的沟槽，所形成的隔离结构与层叠栅极结构自对准，从而通过以下方式提高了存储器件的可靠性避免不及格的问题。

9. 发明授权

US06426250B1 High density stacked MIM capacitor structure 有权
标题翻译：高密度堆叠MIM电容器结构
公开(公告)号：US06426250B1
公开(公告)日：2002-07-30
申请号：US09863225
申请日：2001-05-24
申请人： Tzyh-Cheang Lee , Shyh-Chyi Wong , Chih-Hsien Lin , Chi-Feng Huang
发明人： Tzyh-Cheang Lee , Shyh-Chyi Wong , Chih-Hsien Lin , Chi-Feng Huang
IPC分类号： H01L218242
CPC分类号： H01L28/90 , Y10S438/957
摘要： A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.
摘要翻译：在第一电介质层中形成第一金属插头。产生独立的第二金属插头，其与第一金属插头对准并与第一金属插头接触，延伸第一金属插头。第二个金属插塞由已经在蚀刻停止层和电介质层上形成的开口围绕。电容器电介质层沉积在第一和第二金属插头的暴露表面和围绕第二插头的开口的内表面中。在蚀刻停止层和电介质层的开口内部的电容器电介质上形成一层金属。

10. 发明授权

US09112144B2 Method of fabricating a resistive non-volatile memory device 有权
标题翻译：制造电阻性非易失性存储器件的方法
公开(公告)号：US09112144B2
公开(公告)日：2015-08-18
申请号：US13415705
申请日：2012-03-08
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Tseung-Yuen Tseng , Chih-Yang Lin
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Tseung-Yuen Tseng , Chih-Yang Lin
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/12 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1608
摘要： A method of fabricating a memory cell includes forming a bottom electrode on a substrate, a variable resistive material layer on the bottom electrode, and a top electrode on the variable resistive material layer. A first metal oxide layer interposes the top electrode and the variable resistive material layer. In an embodiment, the first metal oxide layer is a self-formed layer provided by the oxidation of a portion of the top electrode. In an embodiment, a second metal oxide layer is provided interposing the first metal oxide layer and the variable resistive material layer. The second metal oxide may be a self-formed layer formed by the reduction of the variable resistive material layer.
摘要翻译：制造存储单元的方法包括在基板上形成底电极，在底电极上形成可变电阻材料层，以及在可变电阻材料层上形成顶电极。第一金属氧化物层插入顶部电极和可变电阻材料层。在一个实施例中，第一金属氧化物层是由顶部电极的一部分的氧化提供的自形成层。在一个实施例中，设置第二金属氧化物层，其插入第一金属氧化物层和可变电阻材料层。第二金属氧化物可以是通过减少可变电阻材料层而形成的自形成层。

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