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71. 发明授权

US06721853B2 High performance data processing system via cache victimization protocols 失效
标题翻译：高性能数据处理系统通过缓存受害协议
公开(公告)号：US06721853B2
公开(公告)日：2004-04-13
申请号：US09895232
申请日：2001-06-29
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , James Stephen Fields, Jr. , John Steven Dodson
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , James Stephen Fields, Jr. , John Steven Dodson
IPC分类号： G06F1208
CPC分类号： G06F12/0813
摘要： A cache controller for a processor in a remote node of a system bus in a multiway multiprocessor link sends out a cache deallocate address transaction (CDAT) for a given cache line when that cache line is flushed and information from memory in a home node is no longer deemed valid for that cache line of that remote node processor. A local snoop of that CDAT transaction is then performed as a background function by other processors in the same remote node. If the snoop results indicate that same information is valid in another cache, and that cache decides it better to keep it valid in that remote node, then the information remains there. If the snoop results indicate that the information is not valid among caches in that remote node, or will be flushed due to the CDAT, the system memory directory in the home node of the multiprocessor link is notified and changes state in response to this. The system has higher performance due to the cache line maintenance functions being performed in the background rather than based on mainstream demand.
摘要翻译：用于多路多处理器链路中的系统总线的远程节点中的处理器的高速缓存控制器在刷新该高速缓存行并且来自主节点中的存储器的信息为否的时候发送用于给定高速缓存行的缓存解除分配地址事务（CDAT）较长时间被认为对该远程节点处理器的该缓存行有效。然后，该同一远程节点中的其他处理器将执行该CDAT事务的本地侦听作为后台功能。如果窥探结果表明相同的信息在另一个缓存中有效，并且该缓存决定更好地将其保留在该远程节点中，则该信息将保留在该位置。如果窥探结果表明信息在该远程节点的高速缓存中无效，或由于CDAT而被刷新，则通知多处理器链路的家庭节点中的系统内存目录并响应于此改变状态。该系统具有更高的性能，因为高速缓存行维护功能在后台执行，而不是基于主流需求。

72. 发明授权

US06606702B1 Multiprocessor speculation mechanism with imprecise recycling of storage operations 有权
标题翻译：多处理器推测机制，存储操作不正确的回收
公开(公告)号：US06606702B1
公开(公告)日：2003-08-12
申请号：US09588606
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F9312
CPC分类号： G06F9/3842 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/52 , G06F9/522
摘要： Disclosed is a method of operating a processor, by which a speculatively issued load request, which fetches incorrect data, is recycled. An instruction sequence, which includes a barrier instruction and a load instruction that follows the barrier instruction in program order, is received for execution. In response to the barrier instruction, a barrier operation is issued on an interconnect. Following, in response to the load instruction and while the barrier operation is pending, a load request is issued to memory. When a pre-determined type of invalidate, which is affiliated with the load request, is received before the receipt of an acknowledgment for the barrier operation, data that is returned by memory in response to the load request is discarded and the load request is re-issued. The pre-determined type of invalidate includes, for example, a snoop invalidate.
摘要翻译：公开了一种操作处理器的方法，通过该方法，回收了推测性发出的载入请求，其提取不正确的数据。接收指令序列，其中包括按程序顺序跟随障碍指令的障碍指令和加载指令，以执行。响应于屏障指令，在互连上发出屏障操作。接下来，响应于加载指令，并且当屏障操作正在等待时，向存储器发出加载请求。当在接收到屏障操作的确认之前接收到与加载请求相关联的预定类型的无效时，丢弃由存储器响应于加载请求而返回的数据，并且重新加载请求 -发行。预定类型的无效包括例如窥探无效。

73. 发明授权

US06532521B1 Mechanism for high performance transfer of speculative request data between levels of cache hierarchy 失效
标题翻译：在高速缓存层级之间高速传输推测请求数据的机制
公开(公告)号：US06532521B1
公开(公告)日：2003-03-11
申请号：US09345715
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
IPC分类号： G06F1200
CPC分类号： G06F9/3802 , G06F9/30047 , G06F9/383 , G06F12/0811 , G06F12/0862 , G06F12/123 , G06F12/127
摘要： A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hierarchy, and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value. The prefetch limit of cache usage may be established with a maximum number of sets in a congruence class usable by the requesting processing unit. A flag in a directory of the cache may be set to indicate that the prefetch value was retrieved as the result of a prefetch operation. In the implementation wherein the cache is a multi-level cache, a second flag in the cache directory may be set to indicate that prefetch value has been sourced to an upstream cache. A cache line containing prefetch data can be automatically invalidated after a preset amount of time has passed since the prefetch value was requested.
摘要翻译：一种操作计算机系统的处理单元的方法，通过从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。本发明适用于作为操作数数据或指令的值。在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。如果从存储器层次结构请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已经被高速缓存满足，则分配包含较早预取值之一的高速缓存行中的高速缓存行用于接收另一个预取值。高速缓存使用的预取限制可以由请求处理单元可用的同余类中的最大数量的集合来建立。高速缓存目录中的标志可以被设置为指示作为预取操作的结果检索预取值。在其中高速缓存是多级高速缓存的实现中，高速缓存目录中的第二标志可以被设置为指示预取值已经被提供给上游高速缓存。包含预取数据的缓存行可以在从请求预取值开始经过预设的时间后自动失效。

74. 发明授权

US06516404B1 Data processing system having hashed architected processor facilities 失效
标题翻译：数据处理系统散布了架构化的处理器设备
公开(公告)号：US06516404B1
公开(公告)日：2003-02-04
申请号：US09364283
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/30138 , G06F9/3016 , G06F9/384 , G06F12/06 , G06F12/0846
摘要： A processor having a hashed and partitioned register file includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of registers coupled to the execution unit. The plurality of registers are partitioned into a plurality of groups, such that registers within each group can store only data having associated addresses within a respective one of a plurality of subsets of an address space.
摘要翻译：具有散列和分区寄存器文件的处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和耦合到执行单元的多个寄存器。多个寄存器被划分成多个组，使得每个组中的寄存器可以仅存储具有地址空间的多个子集中的相应地址内的相关联地址的数据。

75. 发明授权

US06463507B1 Layered local cache with lower level cache updating upper and lower level cache directories 失效
标题翻译：具有较低级别缓存的分层本地缓存更新上下级缓存目录
公开(公告)号：US06463507B1
公开(公告)日：2002-10-08
申请号：US09340082
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0831 , G06F12/1027
摘要： A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.
摘要翻译：一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。然后可能不精确地重新加载上级（L1）高速缓存（高级缓存也可以不精确地用存储指令重新加载）。低级（L2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。本发明可以应用于例如指令，操作数数据和翻译高速缓存。

76. 发明授权

US06349367B1 Method and system for communication in which a castout operation is cancelled in response to snoop responses 失效
标题翻译：用于通信的方法和系统，其中响应于窥探响应取消了退出操作
公开(公告)号：US06349367B1
公开(公告)日：2002-02-19
申请号：US09368228
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0831 , G06F12/0804
摘要： An effectively “conditional”, cast out operation or cast out portion of a combined operation including a related data access may be cancelled by the combined response to the operation. The combined response logic receives coherency state and/or LRU position information for cache lines corresponding to the cast out victim within snoopers and vertically in-line storage. The combined response logic may also receive information regarding the presence of shared or invalid cache lines in snoopers or lower level storage within the congruence class for the victim, or information regarding the read-once nature of the data access target. Based on these responses, the combined response logic determines whether the cast out should be cancelled and, if so, selects and drives the appropriate combined response code.
摘要翻译：可以通过对操作的组合的响应来取消有效的“有条件”，丢弃包括相关数据访问在内的组合操作的部分。组合的响应逻辑在窥探者和垂直的在线存储器中接收对应于被丢弃的受害者的高速缓存行的相关性状态和/或LRU位置信息。组合的响应逻辑还可以接收关于在受害者的同余类中的窥探者或低级存储器中存在共享或无效高速缓存行的信息，或者关于数据访问目标的一次读取性质的信息。基于这些响应，组合的响应逻辑确定是否应该取消推出，如果是，则选择并驱动适当的组合响应代码。

77. 发明授权

US06279086B1 Multiprocessor system bus with combined snoop responses implicitly updating snooper LRU position 失效
标题翻译：具有组合侦听响应的多处理器系统总线隐式更新snooper LRU位置
公开(公告)号：US06279086B1
公开(公告)日：2001-08-21
申请号：US09368227
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1208
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/123
摘要： Upon snooping a combined data access and cast out/deallocate operation initiating by a horizontal storage device, snoop logic determines, from LRU position information appended to the combined response to the combined operation, whether the coherency state and/or LRU position of the victim may be upgraded within the subject storage device. If so, the coherency state or LRU position is upgraded to improve global data storage management. For instance, a cache line within a snooping storage device may be altered to assume the coherency state of the victim within the storage device initiating the combined operation to improve data storage management under a given replacement policy.
摘要翻译：在窥探组合的数据访问并且通过水平存储设备推出/取消分配操作时，窥探逻辑从附加到对组合操作的组合响应的LRU位置信息确定受害者的相关性状态和/或LRU位置是否可以在主题存储设备内进行升级。如果是这样，则一致性状态或LRU位置被升级以改进全局数据存储管理。例如，可以改变窥探存储设备内的高速缓存行，以假定存储设备内的受害者的一致性状态发起组合操作，以改善给定替换策略下的数据存储管理。

78. 发明授权

US06275909B1 Multiprocessor system bus with system controller explicitly updating snooper cache state information 失效
标题翻译：具有系统控制器的多处理器系统总线显式更新窥探缓存状态信息
公开(公告)号：US06275909B1
公开(公告)日：2001-08-14
申请号：US09368226
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0831 , G06F12/0811
摘要： Combined response logic for a bus receives a combined data access and cast out/deallocate operation initiating by a storage device within a specific level of a storage hierarchy with a coherency state of the cast out/deallocate victim appended. Snoopers on the bus drive snoop responses to the combined operation with the coherency state and/or LRU position of locally-stored cache lines corresponding to the victim appended. The combined response logic determines, from the coherency state information appended to the combined operation and the snoop responses, whether a coherency upgrade is possible. If so, the combined response logic selects a snooper storage device to upgrade the coherency state of a respective cache line corresponding to the victim, and appends an upgrade directive to the combined response. The snooper selected to upgrade the coherency state of a cache line corresponding the victim may be randomly chosen or, as an optimization, be chosen for having the highest LRU position for the respective cache line.
摘要翻译：总线的组合响应逻辑接收组合的数据访问，并且通过存储分层结构的特定级别中的存储设备发起/撤销分配操作，所述存储层级具有附加的转出/取消分配的受害者的一致性状态。总线驱动器侦听器上的侦听器响应于与所附加的受害者对应的本地存储的缓存线的相关性状态和/或LRU位置的组合操作。组合响应逻辑从附加到组合操作和窥探响应的一致性状态信息确定是否可以进行一致性升级。如果是这样，组合的响应逻辑选择窥探存储设备来升级与受害者相对应的相应高速缓存行的一致性状态，并且将升级指令附加到组合响应。选择用于升级与受害者相对应的高速缓存线的相关性状态的窥探者可以被随机选择，或者作为优化被选择以具有用于相应高速缓存行的最高LRU位置。

79. 发明授权

US06249911B1 Optimizing compiler for generating store instructions having memory hierarchy control bits 失效
标题翻译：优化用于生成具有存储器层级控制位的存储指令的编译器
公开(公告)号：US06249911B1
公开(公告)日：2001-06-19
申请号：US09368756
申请日：1999-08-05
申请人： Ravi Kumar Arimilli , John Steve Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steve Dodson , Guy Lynn Guthrie
IPC分类号： G06F1518
CPC分类号： G06F8/4442
摘要： An optimizing compiler for generating STORE instructions having memory hierarchy control bits is disclosed. The compiler first converts a first STORE instruction to a second STORE instruction. The compiler then provides an operation code field within the second instruction for indicating an updating operation. The compiler further provides a vertical write-through level field within the second instruction for indicating a vertical memory level and a horizontal memory level within a multi-level memory hierarchy to which the updating operation should be applied.
摘要翻译：公开了一种用于生成具有存储器层级控制位的存储指令的优化编译器。编译器首先将第一个STORE指令转换为第二个STORE指令。然后，编译器在第二指令内提供用于指示更新操作的操作码字段。编译器进一步提供第二指令内的垂直写通电平字段，用于指示应应用更新操作的多级存储器层级内的垂直存储器级别和水平存储器级别。

80. 发明授权

US06230242B1 Store instruction having vertical memory hierarchy control bits 失效
标题翻译：具有垂直存储器层级控制位的存储指令
公开(公告)号：US06230242B1
公开(公告)日：2001-05-08
申请号：US09368753
申请日：1999-08-05
申请人： Ravi Kumar Arimilli , John Steve Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steve Dodson , Guy Lynn Guthrie
IPC分类号： G06F1314
CPC分类号： G06F9/30043 , G06F9/30047 , G06F12/0804 , G06F12/0811 , G06F12/0897
摘要： A STORE instruction having vertical memory hierarchy control bits is disclosed. The STORE instruction comprises an operation code field, a write-through field, and a vertical write-through level field. The vertical write-through level field indicates a vertical memory level within a memory hierarchy to which the STORE operation should be applied, when the write-through field is set.
摘要翻译：公开了具有垂直存储器层级控制位的STORE指令。 STORE指令包括操作码字段，直通字段和垂直写通电平字段。当直写字段设置时，垂直写入级别字段指示应该应用STORE操作的存储器层次结构内的垂直存储器级别。

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