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1. 发明授权

US06658556B1 Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction 失效
标题翻译：为存储器访问指令散列目标地址，以便在执行之前确定哪个特定的加载/存储单元处理该指令
公开(公告)号：US06658556B1
公开(公告)日：2003-12-02
申请号：US09364288
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1730
CPC分类号： G06F9/3885 , G06F9/3013 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/384 , G06F9/3891
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the data storage and the execution resources, that supplies instructions within the data storage to the execution resources. The execution resources include a plurality of load-store units that each process only instructions that access data having associated addresses within a respective one of a plurality of subsets of an address space. The load-store units can have diverse hardware such that a maximum number of instructions that can be concurrently executed is different for different load-store units or such that some of the load-store units are restricted to executing certain classes of instructions.
摘要翻译：处理器包括执行资源，数据存储和与数据存储器和执行资源耦合的指令排序单元，其将数据存储器内的指令提供给执行资源。执行资源包括多个加载存储单元，每个加载存储单元仅处理在地址空间的多个子集中的相应一个子集内访问具有相关联地址的数据的指令。加载存储单元可以具有不同的硬件，使得可以并发执行的最大数量的指令对于不同的加载存储单元是不同的，或者使得一些加载存储单元被限制为执行某些类别的指令。

2. 发明授权

US06449691B1 Asymmetrical cache properties within a hashed storage subsystem 有权
标题翻译：散列存储子系统内的不对称缓存属性
公开(公告)号：US06449691B1
公开(公告)日：2002-09-10
申请号：US09364285
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0846 , G06F12/0607 , G06F12/0848 , G06F12/0864 , G06F12/0897
摘要： A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, have diverse cache hardware and each preferably store only data having associated addresses within a respective one of a plurality of subsets of an address space. The diverse cache hardware can include, for example, differing cache sizes, differing associativities, differing sectoring, and differing inclusivities.
摘要翻译：处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和在同一级别的多个高速缓存。存储由执行单元使用的数据的高速缓存具有不同的高速缓存硬件，并且每个高速缓存优选仅存储具有地址空间的多个子集中的相应地址内的相关联的地址的数据。不同的高速缓存硬件可以包括例如不同的高速缓存大小，不同的相关性，不同的扇区和不同的包容性。

3. 发明授权

US06253286B1 Apparatus for adjusting a store instruction having memory hierarchy control bits 失效
标题翻译：用于调整具有存储器层级控制位的存储指令的装置
公开(公告)号：US06253286B1
公开(公告)日：2001-06-26
申请号：US09368755
申请日：1999-08-05
申请人： Ravi Kumar Arimilli , John Steve Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steve Dodson , Guy Lynn Guthrie
IPC分类号： G06F1314
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/3834 , G06F11/3409 , G06F12/0811 , G06F12/0837 , G06F2201/86 , G06F2201/87 , G06F2201/88 , G06F2201/885
摘要： An apparatus for adjusting a STORE instruction having memory hierarchy control bits is disclosed. A multiprocessor data processing system includes a multi-level memory hierarchy. The apparatus for adjusting control bits within an instruction to be utilized within the multi-level memory hierarchy comprises a performance monitor and a bit adjuster. The memory hierarchy control bits indicates a memory level within the multi-level memory hierarchy to which an updating operation should be applied. In response to the outputs from the performance monitor, the bit adjuster alters at least one of the memory hierarchy control bits within the instruction in order to achieve optimal performance for the updating operation.
摘要翻译：公开了一种用于调整具有存储器层级控制位的STORE指令的装置。多处理器数据处理系统包括多级存储器层次结构。用于调整要在多级存储器层级内使用的指令内的控制位的装置包括性能监视器和位调节器。存储器层级控制位指示应该应用更新操作的多级存储器层级中的存储器级别。响应于性能监视器的输出，位调整器改变指令内的存储器层级控制位中的至少一个，以便实现更新操作的最佳性能。

4. 发明授权

US06249843B1 Store instruction having horizontal memory hierarchy control bits 失效
标题翻译：具有水平存储器层次控制位的存储指令
公开(公告)号：US06249843B1
公开(公告)日：2001-06-19
申请号：US09368754
申请日：1999-08-05
申请人： Ravi Kumar Arimilli , John Steve Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steve Dodson , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F9/30047 , G06F12/0811 , G06F12/0831
摘要： A STORE instruction having horizontal memory hierarchy control bits is disclosed. The STORE instruction comprises an operation code field, a write-through field, and a horizontal write-through level field. The horizontal write-through level field indicates a horizontal memory level within a multi-level memory hierarchy to which the STORE operation should be applied, when the write-through field is set.
摘要翻译：公开了具有水平存储器层级控制位的STORE指令。 STORE指令包括操作码字段，直写字段和水平写通电平字段。当写入字段被设置时，水平写入级别字段指示应该应用STORE操作的多级存储器层级中的水平存储器级别。

5. 发明授权

US06823471B1 Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem 失效
标题翻译：一种通过可重配置散列存储子系统在数据处理系统内提供高可用性的方法
公开(公告)号：US06823471B1
公开(公告)日：2004-11-23
申请号：US09364281
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1100
CPC分类号： G06F11/20
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing a respective one of a plurality of data streams. If an error is detected in a particular hardware partition, the data stream assigned to that hardware partition is reassigned to another of the plurality of hardware partitions, thus preventing an error in one of the hardware partitions from resulting in a catastrophic failure.
摘要翻译：处理器包括执行资源，数据存储和指令排序单元，其耦合到执行资源和数据存储器，其将数据存储器内的指令提供给执行资源。执行资源，数据存储和指令排序单元中的至少一个由具有用于处理多个数据流中的相应一个的类似功能的多个硬件分区来实现。如果在特定硬件分区中检测到错误，则分配给该硬件分区的数据流被重新分配给多个硬件分区中的另一个，从而防止其中一个硬件分区中的错误导致灾难性故障。

6. 发明授权

US06446165B1 Address dependent caching behavior within a data processing system having HSA (hashed storage architecture) 失效
标题翻译：具有HSA（散列存储架构）的数据处理系统中的依赖于地址的缓存行为
公开(公告)号：US06446165B1
公开(公告)日：2002-09-03
申请号：US09364287
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0811
摘要： A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, each store only data having associated addresses within a respective one of a plurality of subsets of an address space and implement diverse caching behaviors. The diverse caching behaviors can include differing memory update policies, differing coherence protocols, differing prefetch behaviors, and differing cache line replacement policies.
摘要翻译：处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和在同一级别的多个高速缓存。存储由执行单元使用的数据的高速缓存仅存储具有地址空间的多个子集中的相应地址内的相关联地址的数据，并且实现多种缓存行为。不同的缓存行为可以包括不同的内存更新策略，不同的一致性协议，不同的预取行为以及不同的缓存行替换策略。

7. 发明授权

US06598118B1 Data processing system with HSA (hashed storage architecture) 失效
标题翻译：具有HSA（散列存储架构）的数据处理系统
公开(公告)号：US06598118B1
公开(公告)日：2003-07-22
申请号：US09364284
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G60F1200
CPC分类号： G06F12/0864
摘要： A processor having a hashed and partitioned storage subsystem includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a cache subsystem including a plurality of caches that store data utilized by the execution unit. Each cache among the plurality of caches stores only data having associated addresses within a respective one of a plurality of subsets of an address space. In one preferred embodiment, the execution units of the processor include a number of load-store units (LSUs) that each process only instructions that access data having associated addresses within a respective one of the plurality of address subsets. The processor may further be incorporated within a data processing system having a number of interconnects and a number of sets of system memory hardware that each have affinity to a respective one of the plurality of address subsets.
摘要翻译：具有散列和分区存储子系统的处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和包括存储由执行单元使用的数据的多个高速缓存的高速缓存子系统。多个高速缓存中的每个高速缓存仅存储具有地址空间的多个子集中的相应地址内的相关地址的数据。在一个优选实施例中，处理器的执行单元包括多个加载存储单元（LSU），每个加载存储单元仅处理访问在多个地址子集中的相应一个地址子集内具有相关联地址的数据的指令。处理器还可以并入具有多个互连的数据处理系统和多个系统存储器硬件的集合，每个系统存储器硬件各自对多个地址子集中的相应一个具有亲和力。

8. 发明授权

US06516404B1 Data processing system having hashed architected processor facilities 失效
标题翻译：数据处理系统散布了架构化的处理器设备
公开(公告)号：US06516404B1
公开(公告)日：2003-02-04
申请号：US09364283
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/30138 , G06F9/3016 , G06F9/384 , G06F12/06 , G06F12/0846
摘要： A processor having a hashed and partitioned register file includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of registers coupled to the execution unit. The plurality of registers are partitioned into a plurality of groups, such that registers within each group can store only data having associated addresses within a respective one of a plurality of subsets of an address space.
摘要翻译：具有散列和分区寄存器文件的处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和耦合到执行单元的多个寄存器。多个寄存器被划分成多个组，使得每个组中的寄存器可以仅存储具有地址空间的多个子集中的相应地址内的相关联地址的数据。

9. 发明授权

US06249911B1 Optimizing compiler for generating store instructions having memory hierarchy control bits 失效
标题翻译：优化用于生成具有存储器层级控制位的存储指令的编译器
公开(公告)号：US06249911B1
公开(公告)日：2001-06-19
申请号：US09368756
申请日：1999-08-05
申请人： Ravi Kumar Arimilli , John Steve Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steve Dodson , Guy Lynn Guthrie
IPC分类号： G06F1518
CPC分类号： G06F8/4442
摘要： An optimizing compiler for generating STORE instructions having memory hierarchy control bits is disclosed. The compiler first converts a first STORE instruction to a second STORE instruction. The compiler then provides an operation code field within the second instruction for indicating an updating operation. The compiler further provides a vertical write-through level field within the second instruction for indicating a vertical memory level and a horizontal memory level within a multi-level memory hierarchy to which the updating operation should be applied.
摘要翻译：公开了一种用于生成具有存储器层级控制位的存储指令的优化编译器。编译器首先将第一个STORE指令转换为第二个STORE指令。然后，编译器在第二指令内提供用于指示更新操作的操作码字段。编译器进一步提供第二指令内的垂直写通电平字段，用于指示应应用更新操作的多级存储器层级内的垂直存储器级别和水平存储器级别。

10. 发明授权

US06230242B1 Store instruction having vertical memory hierarchy control bits 失效
标题翻译：具有垂直存储器层级控制位的存储指令
公开(公告)号：US06230242B1
公开(公告)日：2001-05-08
申请号：US09368753
申请日：1999-08-05
申请人： Ravi Kumar Arimilli , John Steve Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steve Dodson , Guy Lynn Guthrie
IPC分类号： G06F1314
CPC分类号： G06F9/30043 , G06F9/30047 , G06F12/0804 , G06F12/0811 , G06F12/0897
摘要： A STORE instruction having vertical memory hierarchy control bits is disclosed. The STORE instruction comprises an operation code field, a write-through field, and a vertical write-through level field. The vertical write-through level field indicates a vertical memory level within a memory hierarchy to which the STORE operation should be applied, when the write-through field is set.
摘要翻译：公开了具有垂直存储器层级控制位的STORE指令。 STORE指令包括操作码字段，直通字段和垂直写通电平字段。当直写字段设置时，垂直写入级别字段指示应该应用STORE操作的存储器层次结构内的垂直存储器级别。

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