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71. 发明授权

US07339824B2 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
公开(公告)号：US07339824B2
公开(公告)日：2008-03-04
申请号：US11633326
申请日：2006-12-04
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2216/18 , G11C2216/22 , H01L27/11521 , H01L27/11524
摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

72. 发明授权

US07324384B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07324384B2
公开(公告)日：2008-01-29
申请号：US11442379
申请日：2006-05-26
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/06
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

73. 发明授权

US07283401B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 失效
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07283401B2
公开(公告)日：2007-10-16
申请号：US11391507
申请日：2006-03-28
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04 , G11C5/06 , H01L29/76 , H01L23/544
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
摘要翻译：非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

74. 发明授权

US07177190B2 Combination nonvolatile integrated memory system using a universal technology most suitable for high-density, high-flexibility and high-security sim-card, smart-card and e-passport applications 有权
标题翻译：组合非易失性集成存储系统采用通用技术，最适合高密度，高灵活性和高安全性的SIM卡，智能卡和电子护照应用
公开(公告)号：US07177190B2
公开(公告)日：2007-02-13
申请号：US11025822
申请日：2004-12-24
申请人： Peter W. Lee
发明人： Peter W. Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/04
摘要： A combination EEPROM, NOR-type Flash and NAND-type Flash nonvolatile memory contains memory cells in which a floating gate transistor forms a NAND-type Flash nonvolatile memory cell, forms a NOR-type Flash nonvolatile memory cells and with one or two select transistors forms a two and three transistor EEPROM cell. The nonvolatile memory cells use a large positive programming voltage (+18V) applied to the word lines or select gating lines for programming the memory cells and a large negative erasing voltage (−18V) applied to the word lines or select gating lines for erasing the memory cells. The NOR-type Flash nonvolatile memory array is used to store code of embedded processor programs or application programs for smart cards. The EEPROM array is preferably used to store byte alterable data and NAND-type Flash nonvolatile memory array is used to store personalized biometric data such as Iris, DNA, facial picture and finger prints.
摘要翻译：组合EEPROM，NOR型闪存和NAND型闪存非易失性存储器包含存储单元，其中浮置晶体管形成NAND型闪存非易失性存储单元，形成NOR型闪存非易失性存储单元以及一个或两个选择晶体管形成两个和三个晶体管EEPROM单元。非易失性存储单元使用施加到字线的大的正编程电压（+ 18V）或选择用于编程存储器单元的选通线和施加到字线的大的负擦除电压（-18V）或选择用于擦除的行的选通线记忆细胞 NOR型闪存非易失性存储器阵列用于存储智能卡的嵌入式处理器程序或应用程序的代码。 EEPROM阵列优选用于存储字节可变数据，并且NAND型闪存非易失性存储器阵列用于存储诸如虹膜，DNA，面部图像和指纹之类的个性化生物特征数据。

75. 发明授权

US07110302B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
公开(公告)号：US07110302B2
公开(公告)日：2006-09-19
申请号：US11036868
申请日：2005-01-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

76. 发明授权

US06818491B2 Set of three level concurrent word line bias conditions for a NOR type flash memory array 有权
标题翻译：用于NOR型闪存阵列的三级并发字线偏置条件集
公开(公告)号：US06818491B2
公开(公告)日：2004-11-16
申请号：US10627834
申请日：2003-07-25
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
IPC分类号： H01L218238
CPC分类号： G11C16/3404 , G11C16/0416 , G11C16/344 , H01L27/115 , H01L29/66825
摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.
摘要翻译：在本发明中，示出了在NOR型EEPROM闪速存储器阵列的存储单元操作中使用三个并行字线电压的方法。第一并行字线电压控制在所选择的存储器块内的选定字线上的操作。第二并发字线电压抑制所选存储块中未选择的字线上的单元，并且第三并发字线电压抑制未被选择的块中的未选择的单元从干扰条件。此外，三个连续的字线电压允许块被擦除，块内的页被擦除，并且块内的页被禁止进一步擦除。三个连续的电压还允许检测电池的过度擦除，基于页面的校正，以及验证校正的单元的阈值电压是否高于擦除值但低于擦除值。本文描述的方法产生具有窄电压分布的电池阈值电压。

77. 发明授权

US06788611B2 Flash memory array structure suitable for multiple simultaneous operations 有权
标题翻译：闪存阵列结构适用于多个同时操作
公开(公告)号：US06788611B2
公开(公告)日：2004-09-07
申请号：US10423558
申请日：2003-04-25
申请人： Fu-Chang Hsu , Peter W. Lee , Hsing-Ya Tsao
发明人： Fu-Chang Hsu , Peter W. Lee , Hsing-Ya Tsao
IPC分类号： G11C800
CPC分类号： G11C16/10 , G11C7/18 , G11C8/12 , G11C2216/22
摘要： In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.
摘要翻译：在本发明中公开了一种用于同时读和写操作的闪速存储器。存储器被划分成多个扇区，每个扇区具有扇区解码器。扇区解码器将多个主位线连接到包含在每个存储器扇区中的多个子位线A 2解码器用于演示本发明，尽管包括2解码器和分层式解码器的其他解码器可以使用。存储器阵列可以由各种架构进行配置，包括NOR，OR，NAND，AND，Dual-String和DINOR。存储器单元可以由包括ETOX，FLOTOX，EPROM，EEPROM，分离栅极和PMOS的各种阵列结构形成。

78. 发明授权

US06574152B1 Circuit design for accepting multiple input voltages for flash EEPROM memory operations 有权
标题翻译：用于接受快速EEPROM存储器操作的多个输入电压的电路设计
公开(公告)号：US06574152B1
公开(公告)日：2003-06-03
申请号：US10104736
申请日：2002-03-22
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C700
CPC分类号： G11C16/30 , G11C2207/105 , G11C2207/2227
摘要： In the present invention an EEPROM flash memory is operated using the I/O pins of an EPROM. A novel circuit is used that allows a plurality of voltages to be applied at different times to a single pin designated as CEB (chip enable bar) that permits reading and writing of the flash memory chip. The plurality of voltages can range from a positive voltage, to a ground voltage and to a negative voltage. When a positive voltage like Vdd is applied to the the CEB pin the chip is disabled and entered into a standby mode. When a ground voltage is applied to the CEB pin, the flash memory chip is enabled and a read operation can be performed. When a high negative voltage is applied to the CEB pin, the circuit of the present invention produces an internal high negative voltage to be used for a write operation.
摘要翻译：在本发明中，使用EPROM的I / O引脚来操作EEPROM闪速存储器。使用一种新颖的电路，其允许在不同时间将多个电压施加到指定为允许读取和写入闪存芯片的CEB（芯片使能条）的单个引脚。多个电压可以从正电压到接地电压和负电压的范围。当Vdd等正电压施加到CEB引脚时，芯片被禁止并进入待机模式。当接地电压施加到CEB引脚时，闪存芯片被使能，并且可以执行读操作。当向CEB引脚施加高负电压时，本发明的电路产生用于写入操作的内部高负电压。

79. 发明授权

US6153540A Method of forming phosphosilicate glass having a high wet-etch rate 失效
标题翻译：形成具有高湿蚀刻速率的磷硅酸盐玻璃的方法
公开(公告)号：US6153540A
公开(公告)日：2000-11-28
申请号：US34850
申请日：1998-03-04
申请人： Ishing Lou , Cary Ching , Peter W. Lee , Rong Pan , Paul Gee , Francimar Campana
发明人： Ishing Lou , Cary Ching , Peter W. Lee , Rong Pan , Paul Gee , Francimar Campana
IPC分类号： C23C16/40 , H01L21/316 , H01L21/31
CPC分类号： H01L21/02129 , C23C16/401 , H01L21/02271 , H01L21/31625
摘要： A method and apparatus for controlling the wet-etch rate and thickness uniformity of a dielectric layer, such as a phosphosilicate glass layer (PSG) layer. The method is based upon the discovery that the atmospheric pressure at which a PSG layer is deposited affects the wet-etch rate of the same, during a subsequent processing step, as well as the layer's thickness uniformity. As a result, the method of the present invention includes the step of pressurizing the atmospheric pressure of a semiconductor process chamber within a predetermined range after the substrate is deposited therein. Flowed into the deposition zone is a process gas comprising a silicon source, all oxygen source, and a phosphorous source; and maintaining the deposition zone at process conditions suitable for depositing a phosphosilicate glass layer on the substrate.
摘要翻译：一种用于控制诸如磷硅酸盐玻璃层（PSG）层的介电层的湿蚀刻速率和厚度均匀性的方法和装置。该方法基于以下发现：沉积PSG层的大气压力在随后的处理步骤期间影响其湿蚀刻速率以及层的厚度均匀性。结果，本发明的方法包括在衬底沉积之后在预定范围内对半导体处理室的大气压进行加压的步骤。流入沉积区的是包括硅源，全氧源和磷源的工艺气体; 以及将沉积区保持在适合于在基底上沉积磷硅酸盐玻璃层的工艺条件。

80. 发明授权

US6134150A Erase condition for flash memory 有权
标题翻译：擦除闪存的条件
公开(公告)号：US6134150A
公开(公告)日：2000-10-17
申请号：US360315
申请日：1999-07-23
申请人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter W. Lee , Vei-Han Chan , Hung-Sheng Chen
发明人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter W. Lee , Vei-Han Chan , Hung-Sheng Chen
IPC分类号： G11C16/14 , G11C7/00
CPC分类号： G11C16/14
摘要： In the present invention a flash memory configuration is disclosed that eliminates the need for one of two pump circuits that are commonly required to support an erase function of memory cells on a flash memory chip. The flash memory cells are placed into a triple well structure with a P-well contained within a deep N-well that resides on a P-substrate. The bias voltages for erase of the flash memory cells are chosen so as to require only one voltage pump circuit to be included in the flash memory chip. The chip bias, V.sub.DD, is used for the source of the memory cells and a negative gate voltage is raised in magnitude to maintain the efficiency of the erase operation. The P-well is biased with a negative voltage that is sufficient to prevent the high negative voltage connected to the gate from causing breakdown in word line decoder circuits. The deep N-well and the P-substrate are biased such as to back bias the P/N junctions between the triple well structure.
摘要翻译：在本发明中，公开了一种闪存配置，其不需要通常需要两个泵电路之一来支持闪存芯片上的存储器单元的擦除功能。将闪存单元置于三阱结构中，其中P阱包含在驻留在P基底上的深N阱内。选择用于擦除闪存单元的偏置电压，以便仅需要将一个电压泵电路包括在闪存芯片中。芯片偏置VDD用于存储单元的源极，负栅极电压上升幅度以保持擦除操作的效率。 P阱被施加负电压，该负电压足以防止连接到栅极的高负电压引起字线解码器电路中的击穿。深N阱和P衬底被偏置，以便反向偏置三阱结构之间的P / N结。

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