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1. 发明授权

US06777292B2 Set of three level concurrent word line bias conditions for a NOR type flash memory array 有权
公开(公告)号：US06777292B2
公开(公告)日：2004-08-17
申请号：US10627183
申请日：2003-07-25
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
IPC分类号： H01L21336
CPC分类号： G11C16/3404 , G11C16/0416 , G11C16/344 , H01L27/115 , H01L29/66825
摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

2. 发明授权

US06818491B2 Set of three level concurrent word line bias conditions for a NOR type flash memory array 有权
标题翻译：用于NOR型闪存阵列的三级并发字线偏置条件集
公开(公告)号：US06818491B2
公开(公告)日：2004-11-16
申请号：US10627834
申请日：2003-07-25
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
IPC分类号： H01L218238
CPC分类号： G11C16/3404 , G11C16/0416 , G11C16/344 , H01L27/115 , H01L29/66825
摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.
摘要翻译：在本发明中，示出了在NOR型EEPROM闪速存储器阵列的存储单元操作中使用三个并行字线电压的方法。第一并行字线电压控制在所选择的存储器块内的选定字线上的操作。第二并发字线电压抑制所选存储块中未选择的字线上的单元，并且第三并发字线电压抑制未被选择的块中的未选择的单元从干扰条件。此外，三个连续的字线电压允许块被擦除，块内的页被擦除，并且块内的页被禁止进一步擦除。三个连续的电压还允许检测电池的过度擦除，基于页面的校正，以及验证校正的单元的阈值电压是否高于擦除值但低于擦除值。本文描述的方法产生具有窄电压分布的电池阈值电压。

3. 发明授权

US06620682B1 Set of three level concurrent word line bias conditions for a nor type flash memory array 有权
标题翻译：对于闪存阵列的类型，可以设置三级并发字线偏置条件
公开(公告)号：US06620682B1
公开(公告)日：2003-09-16
申请号：US09978230
申请日：2001-10-16
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
IPC分类号： H01L21336
CPC分类号： G11C16/3404 , G11C16/0416 , G11C16/344 , H01L27/115 , H01L29/66825
摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.
摘要翻译：在本发明中，示出了在NOR型EEPROM闪速存储器阵列的存储单元操作中使用三个并行字线电压的方法。第一并行字线电压控制在所选择的存储器块内的选定字线上的操作。第二并发字线电压抑制所选存储块中未选择的字线上的单元，并且第三并发字线电压抑制未被选择的块中的未选择的单元从干扰条件。此外，三个连续的字线电压允许块被擦除，块内的页被擦除，并且块内的页被禁止进一步擦除。三个连续的电压还允许检测电池的过度擦除，基于页面的校正，以及验证校正的单元的阈值电压是否高于擦除值但低于擦除值。本文描述的方法产生具有窄电压分布的电池阈值电压。

4. 发明授权

US06556481B1 3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell 有权
标题翻译： 3步写操作非易失性半导体单晶体管，非型闪存EEPROM存储单元
公开(公告)号：US06556481B1
公开(公告)日：2003-04-29
申请号：US09852247
申请日：2001-05-09
申请人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter W. Lee , Mervyn Wong
发明人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter W. Lee , Mervyn Wong
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C2216/28
摘要： In the present invention a three step write of a nonvolatile single transistor cell is disclosed. The three steps comprise erasing, reverse programming and programming which can be applied to a plurality of cell types to produce a symmetrical design and allowing shrinkage of the cell beyond that which is possible with other cells designed to use a two step write procedure. The methodology can be applied to either N-channel or P-channel devices and can be used on various type memory cells such as “ETOX”, “NOR” type, “AND” type, and “OR” type. Erasing and programming steps increase the Vt of the cell transistor, whereas reverse programming decreases the Vt of the cell transistor. Over-erase problems are eliminated using the three step write procedure.
摘要翻译：在本发明中，公开了一种非易失性单晶体管单元的三步写入。三个步骤包括擦除，反向编程和编程，其可以应用于多个单元类型以产生对称设计，并且允许单元的收缩超过设计为使用两步写入过程的其他单元可能的缩小。该方法可应用于N沟道或P沟道器件，可用于各种类型的存储单元，例如“ETOX”，“NOR”型，“AND”型和“OR”型。擦除和编程步骤增加了单元晶体管的Vt，而反向编程减小了单元晶体管的Vt。使用三步写入过程可以消除过度擦除问题。

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