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71. 发明授权

US07052937B2 Method and structure for providing improved thermal conduction for silicon semiconductor devices 失效
公开(公告)号：US07052937B2
公开(公告)日：2006-05-30
申请号：US10429758
申请日：2003-05-05
申请人： Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Tsorng-Dih Yuan
发明人： Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Tsorng-Dih Yuan
IPC分类号： H01L21/44
CPC分类号： H01L21/76264 , H01L21/76283 , H01L23/3677 , H01L23/3732 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure. Yet another embodiment comprises diamond sidewalls formed along the device walls in thermal contact with the device junctions to provide heat dissipation through the device junctions to underlying cooling structures. It is also proposed that the foregoing structures, and combinations of the foregoing structures, could be used in conjunction with other known cooling schemes.

72. 发明授权

US07041552B2 Integrated metal-insulator-metal capacitor and metal gate transistor 失效
标题翻译：集成金属 - 绝缘体 - 金属电容器和金属栅极晶体管
公开(公告)号：US07041552B2
公开(公告)日：2006-05-09
申请号：US10787487
申请日：2004-02-26
申请人： Lawrence A. Clevenger , Louis L. Hsu , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Kwong Hon Wong
IPC分类号： H01L21/8242
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28088 , H01L21/28114 , H01L27/0629 , H01L27/10805 , H01L27/1085 , H01L27/10885 , H01L29/42376 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/66545
摘要： An integrated circuit structure is disclosed that comprises a pair of capacitors, each having metal plates separated by an insulator, and metal gate semiconductor transistors electrically connected to the capacitors. The metal gate of the transistors and one of the metal plates of each of the capacitors comprise the same metal level in the integrated circuit structure. More specifically, each of the capacitors comprise a vertical capacitor having an upper metal plate vertically over a lower metal plate and each metal gate of the transistors and each upper metal plate of the capacitors comprise the same metal level in the integrated circuit structure.
摘要翻译：公开了一种集成电路结构，其包括一对电容器，每个电容器具有由绝缘体分隔的金属板和与电容器电连接的金属栅极半导体晶体管。晶体管的金属栅极和每个电容器的金属板之一在集成电路结构中包括相同的金属电平。更具体地，每个电容器包括垂直电容器，其具有垂直于下金属板上的上金属板，并且晶体管的每个金属栅极和电容器的每个上金属板在集成电路结构中包括相同的金属电平。

73. 发明授权

US07038319B2 Apparatus and method to reduce signal cross-talk 失效
标题翻译：降低信号串扰的装置和方法
公开(公告)号：US07038319B2
公开(公告)日：2006-05-02
申请号：US10644372
申请日：2003-08-20
申请人： Patrick H. Buffet , Charles S. Chiu , Jon D. Garlett , Louis L. Hsu , Brian J. Schuh
发明人： Patrick H. Buffet , Charles S. Chiu , Jon D. Garlett , Louis L. Hsu , Brian J. Schuh
IPC分类号： H01L23/48
CPC分类号： H01L23/642 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H01L2924/3025 , H01L2224/05599
摘要： A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal is provided adjacent to the first pair of conductors in the layer, where the first and second pairs of conductors are configured such that cross-talk between the first and second pairs of conductors is substantially minimized, without increasing the size of the package. The height of the first pair of conductors is shorter than the second pair of conductors. Alternatively, the first and second pairs of conductors are configured so that they evenly affect each other. The chip package thus reduces the cross-talk without compromising the density of the interconnections in the package or resulting in an increase in the size of the package.
摘要翻译：公开了一种在载体层中的相邻信号之间的串扰减小的半导体芯片封装。用于承载第一信号的第一对导体提供在载体的层中。用于承载第二信号的第二对导体被提供为邻近层中的第一对导体，其中第一和第二对导体被配置为使得第一和第二对导体之间的串扰基本上最小化，而不会增加包装的尺寸。第一对导体的高度比第二对导体短。或者，第一和第二对导体被配置成使得它们彼此均匀地影响。芯片封装因此减少串扰，而不会影响封装中互连的密度，或导致封装尺寸的增加。

74. 发明授权

US07029956B2 Memory system capable of operating at high temperatures and method for fabricating the same 失效
公开(公告)号：US07029956B2
公开(公告)日：2006-04-18
申请号：US10666972
申请日：2003-09-19
申请人： Louis L. Hsu , Li-Kong Wang
发明人： Louis L. Hsu , Li-Kong Wang
IPC分类号： H01L21/332
CPC分类号： H01L27/1027 , H01L21/8213 , H01L27/0605 , Y10S438/931
摘要： A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

75. 发明授权

US06933189B2 Integration system via metal oxide conversion 失效
标题翻译：集成系统通过金属氧化物转换
公开(公告)号：US06933189B2
公开(公告)日：2005-08-23
申请号：US10870382
申请日：2004-06-16
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
IPC分类号： H01L21/285 , H01L21/30 , H01L21/306 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/8232 , H01L21/8234 , H01L29/49 , H01L29/76 , H01L29/78 , H01L29/84 , H01L31/062 , H01L31/107 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4983 , H01L21/28194 , H01L21/28518 , H01L21/28568 , H01L21/3003 , H01L21/76823 , H01L21/76895 , H01L29/517 , H01L29/7833
摘要： A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a portion of the first insulator into a metallic film, converting the metallic film into one of a silicide and a salicide film, forming an interconnect region above the trench region, forming an etch stop layer above the first insulator, the trench region, the gate electrode, and the pair of insulating spacers, forming a second insulator above the etch stop layer, and forming contacts in the second insulator. The first insulator comprises a metal oxide material, which comprises one of a HfOx and a ZrOx.
摘要翻译：晶体管器件的方法和结构包括在衬底中形成源极，漏极和沟槽区域，在衬底上形成第一绝缘体，在第一绝缘体之上形成栅电极，形成邻接电极的一对绝缘衬垫，转换将所述第一绝缘体的一部分转变为金属膜，将所述金属膜转化成硅化物和自对隔硅膜之一，在所述沟槽区上方形成互连区，在所述第一绝缘体上方形成蚀刻停止层，所述沟槽区，所述栅电极和一对绝缘间隔物，在蚀刻停止层上方形成第二绝缘体，并在第二绝缘体中形成接触。第一绝缘体包括金属氧化物材料，其包括HfO x x和ZrO x x之一。

76. 发明授权

US06911375B2 Method of fabricating silicon devices on sapphire with wafer bonding at low temperature 失效
标题翻译：在低温下用蓝宝石制造硅器件的方法
公开(公告)号：US06911375B2
公开(公告)日：2005-06-28
申请号：US10452715
申请日：2003-06-02
申请人： Kathryn W. Guarini , Louis L. Hsu , Leathen Shi , Dinkar V. Singh , Li-Kong Wang
发明人： Kathryn W. Guarini , Louis L. Hsu , Leathen Shi , Dinkar V. Singh , Li-Kong Wang
IPC分类号： H01L21/30 , H01L21/68 , H01L21/762
CPC分类号： H01L21/76256 , H01L21/6835 , H01L21/76254 , H01L2221/68368 , H01L2924/19041
摘要： Described is a method for making silicon on sapphire structures, and devices therefrom. The inventive method of forming integrated circuits on a sapphire substrate comprises the steps of providing a device layer on an oxide layer of a temporary substrate; bonding the device layer to a handling substrate; removing the temporary substrate to provide a structure containing the device layer between the oxide layer and the handling substrate; bonding a sapphire substrate to the oxide layer; removing the handling substrate from the structure; and annealing the final structure to provide a substrate comprising the oxide layer between the device layer and the sapphire substrate. The sapphire substrate may comprise bulk sapphire or may be a conventional substrate material with an uppermost sapphire layer.
摘要翻译：描述了在蓝宝石结构上制造硅的方法及其装置。在蓝宝石衬底上形成集成电路的本发明的方法包括以下步骤：在临时衬底的氧化物层上提供器件层; 将所述器件层接合到处理衬底; 去除所述临时衬底以提供在所述氧化物层和所述处理衬底之间包含所述器件层的结构; 将蓝宝石衬底结合到氧化物层; 从结构中去除处理基板; 并退火最终结构以提供包括在器件层和蓝宝石衬底之间的氧化物层的衬底。蓝宝石衬底可以包括散装蓝宝石，或者可以是具有最上层蓝宝石层的常规衬底材料。

77. 发明授权

US06869895B1 Method for adjusting capacitance of an on-chip capacitor 失效
标题翻译：调整片上电容器电容的方法
公开(公告)号：US06869895B1
公开(公告)日：2005-03-22
申请号：US10674719
申请日：2003-09-30
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01G4/255 , H01L21/02 , H01L21/66 , H01L21/31
CPC分类号： H01G4/255 , H01L22/22 , H01L28/40
摘要： A method and apparatus for adjusting capacitance of an on-chip capacitor uses exposure of a dielectric material of the capacitor to an ion beam comprising ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译：用于调整片上电容器的电容的方法和装置使用将电容器的电介质材料暴露于包含至少一种材料的离子的离子束，以改变介电材料的介电常数。

78. 发明授权

US06781185B2 Semiconductor high dielectric constant decoupling capacitor structures and process for fabrication 有权
标题翻译：半导体高介电常数去耦电容器结构及其制造工艺
公开(公告)号：US06781185B2
公开(公告)日：2004-08-24
申请号：US10091193
申请日：2002-03-05
申请人： Howard Hao Chen , Louis L. Hsu , Li-Kong Wang
发明人： Howard Hao Chen , Louis L. Hsu , Li-Kong Wang
IPC分类号： H01L27108
CPC分类号： H01L28/91 , H01L23/5222 , H01L27/0805 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： Apparatus and method for providing high dielectric constant decoupling capacitors for semiconductor structures. The high dielectric constant decoupling capacitor can be fabricated by depositing high dielectric constant material between adjacent conductors on the same level, between conductors in successive levels, or both, to thereby provide very large capacitance value without any area or reliability penalty.
摘要翻译：用于为半导体结构提供高介电常数去耦电容器的装置和方法。高介电常数去耦电容器可以通过在相同电平上的相邻导体之间，连续电平的导体之间沉积高介电常数材料或两者来制造，从而提供非常大的电容值而没有任何面积或可靠性损失。

79. 发明授权

US06775736B2 Embedded DRAM system having wide data bandwidth and data transfer data protocol 有权
标题翻译：具有宽数据带宽和数据传输数据协议的嵌入式DRAM系统
公开(公告)号：US06775736B2
公开(公告)日：2004-08-10
申请号：US10062812
申请日：2002-01-31
申请人： Louis L. Hsu , Rajiv J. Joshi , Jeremy K. Stephens , Daniel W. Storaska
发明人： Louis L. Hsu , Rajiv J. Joshi , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： G06F1200
CPC分类号： G11C7/1048 , G06F13/4243 , G11C5/063 , G11C11/4096 , G11C29/846 , G11C2207/104
摘要： A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths. The data communication system includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data to or from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation.
摘要翻译：一种具有多个数据路径的宽数据宽度半导体存储器系统的自定时数据通信系统。数据通信系统包括被配置为存储数据的多个数据库，其中多个数据库中的相应数据库连接到多个数据路径中相应的一个数据路径。数据通信系统还包括用于根据接收到指示数据传送操作已被启动以用于将数据传送到相应的一个数据路径或从相应的一个数据路径传送数据的监视信号来控制相应的一个数据路径的电路。用于控制的电路包括用于产生控制信号的电路，该控制信号用于在传送数据以准备随后的数据传送操作之后控制相应的一个数据路径的复位。

80. 发明授权

US06751152B2 Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage 失效
标题翻译：方法和配置允许在增加具有存取晶体管阈值电压的感测信号的同时降低字线升压电压操作
公开(公告)号：US06751152B2
公开(公告)日：2004-06-15
申请号：US09999379
申请日：2001-10-31
申请人： Louis L. Hsu , Toshiaki K. Kirihata , Daniel W. Storaska
发明人： Louis L. Hsu , Toshiaki K. Kirihata , Daniel W. Storaska
IPC分类号： G11C800
CPC分类号： G11C11/4085 , G11C7/065 , G11C11/4091
摘要： A memory array architecture employs a full Vdd bitline precharged voltage and a low wordline boost voltage, which is less than Vdd plus the threshold voltage of the access transistor. In a write mode, a first low level of a data bit is almost fully written to a storage element, however a second high level of the data bit is not fully written to the storage element. In a read mode, the first low level of the data bit is fully read out from the storage element, however the second high level of the data bit is not read out by utilizing the access transistor threshold voltage. This allows a sensing signal only with the first voltage level transfer to the Vdd precharged BL. A reference WL is preferably used for generating a reference bitline voltage for a differential Vdd sensing scheme. Alternatively, a single BL digital sensing scheme may be used. Lowering the wordline voltage results in a reduction in power consumption by saving power on Vpp generator and support circuits, and a reduction in the size of the Vpp generator and support circuits, and also eliminates high Vpp voltage related problems such as dielectric breakdown and other reliability concerns while avoiding a complex decoding scheme and saving cost.
摘要翻译：存储器阵列架构采用全Vdd位线预充电电压和低字线升压电压，其小于Vdd加上存取晶体管的阈值电压。在写入模式中，数据位的第一低电平几乎完全写入存储元件，然而数据位的第二高电平未完全写入存储元件。在读取模式下，数据位的第一低电平从存储元件完全读出，然而数据位的第二高电平不通过利用存取晶体管阈值电压被读出。这允许感测信号仅在第一电压电平传输到Vdd预充电BL。参考WL优选地用于产生用于差分Vdd感测方案的参考位线电压。或者，可以使用单个BL数字感测方案。降低字线电压通过节省Vpp发生器和支持电路上的功率以及减小Vpp发生器和支持电路的尺寸而降低功耗，并且消除了与Vpp电压相关的高电压问题，例如介质击穿和其他可靠性同时避免复杂的解码方案并节省成本。

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