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1. 发明授权

US08288826B2 Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) 有权
标题翻译：绝缘体上半导体（SOI）结构包括梯度氮化掩埋氧化物（BOX）
公开(公告)号：US08288826B2
公开(公告)日：2012-10-16
申请号：US13290634
申请日：2011-11-07
申请人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
发明人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
IPC分类号： H01L29/76 , H01L21/00
CPC分类号： H01L29/78603 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
摘要翻译：绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。

2. 发明授权

US08053373B2 Semiconductor-on-insulator(SOI) structures including gradient nitrided buried oxide (BOX) 有权
标题翻译：绝缘体上半导体（SOI）结构包括梯度氮化掩埋氧化物（BOX）
公开(公告)号：US08053373B2
公开(公告)日：2011-11-08
申请号：US12123706
申请日：2008-05-20
申请人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
发明人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
IPC分类号： H01L21/31 , H01L29/76
CPC分类号： H01L29/78603 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
摘要翻译：绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。

3. 发明申请

US20080014740A1 Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) 有权
公开(公告)号：US20080014740A1
公开(公告)日：2008-01-17
申请号：US11483901
申请日：2006-07-10
申请人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
发明人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
IPC分类号： H01L21/4763
CPC分类号： H01L29/78603 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

4. 发明授权

US07566631B2 Low temperature fusion bonding with high surface energy using a wet chemical treatment 失效
标题翻译：使用湿化学处理的低表面能低温熔接
公开(公告)号：US07566631B2
公开(公告)日：2009-07-28
申请号：US11411395
申请日：2006-04-26
申请人： Kevin K. Chan , Kathryn Wilder Guarini , Erin C. Jones , Antonio F. Saavedra, Jr. , Leathen Shi , Dinkar V. Singh
发明人： Kevin K. Chan , Kathryn Wilder Guarini , Erin C. Jones , Antonio F. Saavedra, Jr. , Leathen Shi , Dinkar V. Singh
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/02052 , H01L21/02164 , H01L21/02343 , H01L21/2007 , H01L21/306 , H01L21/3105 , H01L21/31612 , H01L21/31662 , H01L21/76251
摘要： Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.
摘要翻译：描述了涉及NH 4 OH的湿化学表面处理，其能够在低温（小于或等于400℃）下将诸如半导体（例如Si）的两个晶片极度直接结合到绝缘体（例如SiO 2）。使用这些表面处理中的一些已经实现了接合界面的高达〜4835±675mJ / m 2的表面能。该值与显着更高的处理温度（小于1000℃）报告的值相当。这里也可以实现具有优异产率和约2500mJ / m 2的表面能的无空隙结合界面。

5. 发明申请

US20090045462A1 ULTRATHIN SOI CMOS DEVICES EMPLOYING DIFFERENTIAL STI LINERS 失效
标题翻译： ULTRATHIN SOI CMOS器件采用差分STI衬线
公开(公告)号：US20090045462A1
公开(公告)日：2009-02-19
申请号：US11839272
申请日：2007-08-15
申请人： Zhibin Ren , Ghavam Shahidi , Dinkar V. Singh , Jeffrey W. Sleight , Xinhui Wang
发明人： Zhibin Ren , Ghavam Shahidi , Dinkar V. Singh , Jeffrey W. Sleight , Xinhui Wang
IPC分类号： H01L21/8238 , H01L27/12
CPC分类号： H01L21/84 , H01L21/76229 , H01L21/76283 , H01L27/1203 , H01L29/7846
摘要： An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.
摘要翻译：在包含硅的顶部半导体层的超薄绝缘体上的基板上形成氧氮化物衬垫层和掩模层。浅沟槽的第一部分通过NFET区域和蚀刻的光刻掩模在顶部半导体层中图案化，其中埋入绝缘体层的暴露部分凹陷并且顶部半导体层被切割。在PFET有源区的暴露的侧壁和底部周边表面上形成厚的热氧化硅衬垫以施加高横向压应力。浅沟槽的第二部分通过包括PFET有源区的PFET区域的光刻掩模形成。在NFET有源区的暴露的侧壁上形成薄的热氧化硅或不存在热氧化硅，其经受低的侧向压应力或没有横向压应力。

6. 发明授权

US06911375B2 Method of fabricating silicon devices on sapphire with wafer bonding at low temperature 失效
标题翻译：在低温下用蓝宝石制造硅器件的方法
公开(公告)号：US06911375B2
公开(公告)日：2005-06-28
申请号：US10452715
申请日：2003-06-02
申请人： Kathryn W. Guarini , Louis L. Hsu , Leathen Shi , Dinkar V. Singh , Li-Kong Wang
发明人： Kathryn W. Guarini , Louis L. Hsu , Leathen Shi , Dinkar V. Singh , Li-Kong Wang
IPC分类号： H01L21/30 , H01L21/68 , H01L21/762
CPC分类号： H01L21/76256 , H01L21/6835 , H01L21/76254 , H01L2221/68368 , H01L2924/19041
摘要： Described is a method for making silicon on sapphire structures, and devices therefrom. The inventive method of forming integrated circuits on a sapphire substrate comprises the steps of providing a device layer on an oxide layer of a temporary substrate; bonding the device layer to a handling substrate; removing the temporary substrate to provide a structure containing the device layer between the oxide layer and the handling substrate; bonding a sapphire substrate to the oxide layer; removing the handling substrate from the structure; and annealing the final structure to provide a substrate comprising the oxide layer between the device layer and the sapphire substrate. The sapphire substrate may comprise bulk sapphire or may be a conventional substrate material with an uppermost sapphire layer.
摘要翻译：描述了在蓝宝石结构上制造硅的方法及其装置。在蓝宝石衬底上形成集成电路的本发明的方法包括以下步骤：在临时衬底的氧化物层上提供器件层; 将所述器件层接合到处理衬底; 去除所述临时衬底以提供在所述氧化物层和所述处理衬底之间包含所述器件层的结构; 将蓝宝石衬底结合到氧化物层; 从结构中去除处理基板; 并退火最终结构以提供包括在器件层和蓝宝石衬底之间的氧化物层的衬底。蓝宝石衬底可以包括散装蓝宝石，或者可以是具有最上层蓝宝石层的常规衬底材料。

7. 发明申请

US20120049317A1 SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX) 有权
标题翻译：半导体绝缘体（SOI）结构，包括梯度氮化氧化物（BOX）
公开(公告)号：US20120049317A1
公开(公告)日：2012-03-01
申请号：US13290634
申请日：2011-11-07
申请人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
发明人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
IPC分类号： H01L29/12
CPC分类号： H01L29/78603 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
摘要翻译：绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。

8. 发明授权

US07713837B2 Low temperature fusion bonding with high surface energy using a wet chemical treatment 失效
标题翻译：使用湿化学处理的低表面能低温熔接
公开(公告)号：US07713837B2
公开(公告)日：2010-05-11
申请号：US12128259
申请日：2008-05-28
申请人： Kevin K. Chan , Kathryn Wilder Guarini , Erin C. Jones , Antonio F. Saavedra, Jr. , Leathen Shi , Dinkar V. Singh
发明人： Kevin K. Chan , Kathryn Wilder Guarini , Erin C. Jones , Antonio F. Saavedra, Jr. , Leathen Shi , Dinkar V. Singh
IPC分类号： H01L21/30
CPC分类号： H01L21/02052 , H01L21/02164 , H01L21/02343 , H01L21/2007 , H01L21/306 , H01L21/3105 , H01L21/31612 , H01L21/31662 , H01L21/76251
摘要： Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.
摘要翻译：描述了涉及NH 4 OH的湿化学表面处理，其能够在低温（小于或等于400℃）下将诸如半导体（例如Si）的两个晶片极度直接结合到绝缘体（例如SiO 2）。使用这些表面处理中的一些已经实现了接合界面的高达〜4835±675mJ / m 2的表面能。该值与显着更高的处理温度（小于1000℃）报告的值相当。本发明还可以实现具有优异的产率和表面能的约200mJ / m 2的无空隙结合界面。

9. 发明授权

US08021956B2 Ultrathin SOI CMOS devices employing differential STI liners 失效
标题翻译：使用差分STI衬垫的超薄SOI CMOS器件
公开(公告)号：US08021956B2
公开(公告)日：2011-09-20
申请号：US12652918
申请日：2010-01-06
申请人： Zhibin Ren , Ghavam Shahidi , Dinkar V. Singh , Jeffrey W. Sleight , Xinhui Wang
发明人： Zhibin Ren , Ghavam Shahidi , Dinkar V. Singh , Jeffrey W. Sleight , Xinhui Wang
IPC分类号： H01L21/76
CPC分类号： H01L21/84 , H01L21/76229 , H01L21/76283 , H01L27/1203 , H01L29/7846
摘要： An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.
摘要翻译：在包含硅的顶部半导体层的超薄绝缘体上的基板上形成氧氮化物衬垫层和掩模层。浅沟槽的第一部分通过NFET区域和蚀刻的光刻掩模在顶部半导体层中图案化，其中埋入绝缘体层的暴露部分凹陷并且顶部半导体层被切割。在PFET有源区的暴露的侧壁和底部周边表面上形成厚的热氧化硅衬垫以施加高横向压应力。浅沟槽的第二部分通过包括PFET有源区的PFET区域的光刻掩模形成。在NFET有源区的暴露的侧壁上形成薄的热氧化硅或不存在热氧化硅，其经受低的侧向压应力或没有横向压应力。

10. 发明申请

US20100105187A1 ULTRATHIN SOI CMOS DEVICES EMPLOYING DIFFERENTIAL STI LINERS 失效
标题翻译： ULTRATHIN SOI CMOS器件采用差分STI衬线
公开(公告)号：US20100105187A1
公开(公告)日：2010-04-29
申请号：US12652918
申请日：2010-01-06
申请人： Zhibin Ren , Ghavam Shahidi , Dinkar V. Singh , Jeffrey W. Sleight , Xinhui Wang
发明人： Zhibin Ren , Ghavam Shahidi , Dinkar V. Singh , Jeffrey W. Sleight , Xinhui Wang
IPC分类号： H01L21/762
CPC分类号： H01L21/84 , H01L21/76229 , H01L21/76283 , H01L27/1203 , H01L29/7846
摘要： An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.
摘要翻译：在包含硅的顶部半导体层的超薄绝缘体上的基板上形成氧氮化物衬垫层和掩模层。浅沟槽的第一部分通过NFET区域和蚀刻的光刻掩模在顶部半导体层中图案化，其中埋入绝缘体层的暴露部分凹陷并且顶部半导体层被切割。在PFET有源区的暴露的侧壁和底部周边表面上形成厚的热氧化硅衬垫以施加高横向压应力。浅沟槽的第二部分通过包括PFET有源区的PFET区域的光刻掩模形成。在NFET有源区的暴露的侧壁上形成薄的热氧化硅或不存在热氧化硅，其经受低的侧向压应力或没有横向压应力。

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