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71. 发明授权

US07648880B2 Nitride-encapsulated FET (NNCFET) 失效
标题翻译：氮化物封装的FET（NNCFET）
公开(公告)号：US07648880B2
公开(公告)日：2010-01-19
申请号：US12142394
申请日：2008-06-19
申请人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
发明人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。在本发明中，提供自对准隔离区以减小DGFET结构中的寄生电容。此外，本发明封装了含硅沟道层，使背栅能够被更大程度地氧化，从而进一步降低结构的寄生电容。

72. 发明授权

US07507989B2 Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) 有权
公开(公告)号：US07507989B2
公开(公告)日：2009-03-24
申请号：US11927006
申请日：2007-10-29
申请人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
发明人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
IPC分类号： H01L29/06
CPC分类号： H01L29/78687 , H01L21/2007 , H01L29/1054 , H01L29/517 , H01L29/66742 , H01L29/7833 , H01L29/7842 , H01L29/78603
摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

73. 发明申请

US20080251813A1 HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS 审中-公开
标题翻译： HETERO-INTEGRATED应变硅n-和p- MOSFET
公开(公告)号：US20080251813A1
公开(公告)日：2008-10-16
申请号：US12140612
申请日：2008-06-17
申请人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
发明人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
IPC分类号： H01L29/778
CPC分类号： H01L21/26506 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/26513 , H01L21/823807 , H01L29/1054 , H01L29/7842 , Y10S438/938
摘要： The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.
摘要翻译：本发明提供半导体结构和制造用于施加MOSFET器件的这种结构的方法。以这样的方式制造半导体结构，使得制造n-MOSFET的晶片区域中的层结构不同于制造p-MOSFET的晶片的区域中的层结构。通过首先通过离子注入诸如He的光原子形成具有含Si衬底的表面的损伤区域来制造结构。然后在含有受损区域的含Si衬底上形成应变SiGe合金。然后采用退火步骤通过缺陷引发的应变弛豫引起应变SiGe合金的显着松弛。接下来，在弛豫的SiGe合金上形成诸如应变Si的应变半导体盖。

74. 发明申请

US20080200021A1 SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK 失效
标题翻译：分散多晶硅/多晶硅合金栅极堆叠
公开(公告)号：US20080200021A1
公开(公告)日：2008-08-21
申请号：US12104570
申请日：2008-04-17
申请人： Kevin K. Chan , Jia Chen , Shih-Fen Huang , Edward J. Nowak
发明人： Kevin K. Chan , Jia Chen , Shih-Fen Huang , Edward J. Nowak
IPC分类号： H01L21/3205
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
摘要翻译：在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4A厚的界面层。薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。栅电极堆叠结构用于nFET和pFET两者。

75. 发明授权

US07402466B2 Strained silicon CMOS on hybrid crystal orientations 有权
标题翻译：应变硅CMOS在混合晶体取向上
公开(公告)号：US07402466B2
公开(公告)日：2008-07-22
申请号：US11492271
申请日：2006-07-25
申请人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
发明人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

76. 发明授权

US07361611B2 Doped nitride film, doped oxide film and other doped films 有权
标题翻译：掺杂氮化物膜，掺杂氧化物膜等掺杂膜
公开(公告)号：US07361611B2
公开(公告)日：2008-04-22
申请号：US11349233
申请日：2006-02-08
申请人： Ashima B. Chakravarti , Judson Holt , Kevin K. Chan , Sadanand V. Deshpande , Rangarajan Jagannathan
发明人： Ashima B. Chakravarti , Judson Holt , Kevin K. Chan , Sadanand V. Deshpande , Rangarajan Jagannathan
IPC分类号： H01L21/31
CPC分类号： H01L29/7843 , C23C16/308 , C23C16/34 , C23C16/401 , H01L21/0214 , H01L21/0217 , H01L21/02271 , H01L21/3143 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/31608 , H01L21/31612 , H01L21/3185 , H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L29/7833 , H01L29/78675
摘要： Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.
摘要翻译：在形成氮化硅，氧化硅，氮氧化硅或碳化硅膜期间添加至少一种非硅前体（例如锗前体，碳前体等）改善了沉积速率和/或使得可以调谐性能的电影，如调整电影的压力。此外，在掺杂的氧化硅或掺杂氮化硅或其它掺杂结构中，掺杂剂的存在可用于测量与掺杂剂相关的信号，作为蚀刻停止或用于在蚀刻期间实现控制。

77. 发明授权

US07087965B2 Strained silicon CMOS on hybrid crystal orientations 失效
公开(公告)号：US07087965B2
公开(公告)日：2006-08-08
申请号：US10830347
申请日：2004-04-22
申请人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
发明人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

78. 发明授权

US06946696B2 Self-aligned isolation double-gate FET 有权
标题翻译：自对准隔离双栅极FET
公开(公告)号：US06946696B2
公开(公告)日：2005-09-20
申请号：US10328285
申请日：2002-12-23
申请人： Kevin K. Chan , Guy M. Cohen , Meikei Ieong , Ronnen A. Roy , Paul Solomon , Min Yang
发明人： Kevin K. Chan , Guy M. Cohen , Meikei Ieong , Ronnen A. Roy , Paul Solomon , Min Yang
IPC分类号： H01L29/417 , H01L21/02 , H01L21/265 , H01L21/336 , H01L21/76 , H01L21/762 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786 , H01C27/148
CPC分类号： H01L29/66484 , H01L21/26533 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66772 , H01L29/7831 , H01L29/7834 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。提供了两种降低源极/漏极区下寄生电容的新手段。首先，栅极外部的硅区域被转换为氧化物，同时用第一间隔物保护邻近栅极的硅凸缘。使用自对准氧植入物或某些其它物种的植入物可以促进氧化。其次，去除第一间隔物，用第二间隔物代替，通过采用横向选择性外延生长并使用现在暴露的硅壁缘作为种子，在自对准氧化物隔离区域上生长新的硅源/漏区。这实现了对背板的低电容，同时保持阈值电压的控制。

79. 发明授权

US06916694B2 Strained silicon-channel MOSFET using a damascene gate process 失效
标题翻译：应变硅沟道MOSFET使用镶嵌栅极工艺
公开(公告)号：US06916694B2
公开(公告)日：2005-07-12
申请号：US10650400
申请日：2003-08-28
申请人： Hussein I. Hanafi , David J. Frank , Kevin K. Chan
发明人： Hussein I. Hanafi , David J. Frank , Kevin K. Chan
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/66545 , H01L29/665 , H01L29/66537 , H01L29/7842 , Y10S438/938
摘要： The present invention provides a method using a damascene-gate process to improve the transport properties of FETs through strain Si. Changes in mobility and FET characteristics are deliberately made in a Si or silicon-on-insulator (SOI) structure through the introduction of local strain in the channel region, without introducing strain in the device source and drain regions. The method has the advantage of not straining the source and drain regions resulting in very low leakage junctions and also it does not require any special substrate preparation like the case of a strained Si/relaxed SiGe system. Moreover, the method is compatible with existing mainstream CMOS processing. The present invention also provides a CMOS device that has a localized strained Si channel that is formed using the method of the present invention.
摘要翻译：本发明提供了一种使用镶嵌栅极工艺来改善FET通过应变Si的传输特性的方法。迁移率和FET特性的变化是通过在沟道区域中引入局部应变而在Si或绝缘体上硅（SOI）结构中作出的，而不会在器件源极和漏极区域引入应变。该方法的优点是不会使源极和漏极区域产生非常低的泄漏接头，并且也不需要像应变Si /弛豫SiGe系统那样的任何特殊的衬底制备。此外，该方法与现有的主流CMOS处理兼容。本发明还提供一种CMOS器件，其具有使用本发明的方法形成的局部应变Si沟道。

80. 发明授权

US06841831B2 Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process 有权
标题翻译：使用凹陷通道镶嵌栅极工艺，具有低源极和漏极电阻以及最小重叠电容的全耗尽SOI MOSFET
公开(公告)号：US06841831B2
公开(公告)日：2005-01-11
申请号：US10461821
申请日：2003-06-13
申请人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
发明人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
IPC分类号： H01L21/336 , H01L29/786 , H01L29/76
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78612
摘要： A sub-0.05 μm channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 μm channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.
摘要翻译：提供了具有低源极和漏极电阻以及最小重叠电容的0.05微米通道长度的全耗尽SOI MOSFET器件及其制造方法。子0.05通道长度全耗尽的SOI MOSFET器件包括SOI结构，其至少包含具有第一厚度的沟道区和邻接其中存在第二厚度的源极/漏极区的SOI层，其中第二厚度为大于第一厚度，并且源/漏区具有存在于其上的自对准硅化物层。栅极区也存在于SOI层的顶部。

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