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71. 发明申请

US20130087639A1 Electromagnetic Fuel Injection Valve 有权
标题翻译：电磁燃油喷射阀
公开(公告)号：US20130087639A1
公开(公告)日：2013-04-11
申请号：US13638382
申请日：2011-04-01
申请人： Hirotaka Nakai , Motoyuki Abe , Toru Ishikawa , Yasuo Namaizawa , Nobuaki Kobayashi , Kiyoshi Yoshii , Hitoshi Furudate
发明人： Hirotaka Nakai , Motoyuki Abe , Toru Ishikawa , Yasuo Namaizawa , Nobuaki Kobayashi , Kiyoshi Yoshii , Hitoshi Furudate
IPC分类号： F02M51/06
CPC分类号： F02M51/061 , F02M51/0671 , F02M51/0685 , F02M61/20 , F02M2200/306
摘要： An electromagnetic fuel injection valve includes: a valve element which closes a fuel passage by coming into contact with a valve seat and opens the fuel passage by going away from the valve seat; an electromagnet which includes a coil and a magnetic core formed as a drive portion for driving the valve element; a movable element which is held by the valve element in a state where the movable element is displaceable in the direction of a drive force of the valve element relative to the valve element; a first biasing portion for biasing the valve element in the direction opposite to the direction of a drive force generated by the drive portion; a second biasing portion for biasing the movable element in the direction of the drive force with a biasing force smaller than the biasing force generated by the first biasing portion; and a restricting portion for restricting the displacement of the movable element in the direction of the drive force relative to the valve element.
摘要翻译：电磁燃料喷射阀包括：阀元件，其通过与阀座接触并关闭燃料通道并通过远离阀座打开燃料通道; 电磁体，其包括形成为驱动阀元件的驱动部的线圈和磁芯; 可移动元件，其在所述可移动元件可相对于所述阀元件的驱动力相对于所述阀元件的方向移动的状态下被所述阀元件保持; 第一偏压部分，用于沿与驱动部分产生的驱动力的方向相反的方向偏压阀元件; 第二偏置部分，用于利用小于由第一偏压部分产生的偏压力的偏压力来使驱动力方向偏压可动元件; 以及用于限制可动元件相对于阀元件的驱动力方向的位移的限制部。

72. 发明授权

US08230839B2 Fuel injection valve 有权
标题翻译：燃油喷射阀
公开(公告)号：US08230839B2
公开(公告)日：2012-07-31
申请号：US12438668
申请日：2006-09-25
申请人： Masahiko Hayatani , Motoyuki Abe , Toru Ishikawa , Eiichi Kubota , Takehiko Kowatari
发明人： Masahiko Hayatani , Motoyuki Abe , Toru Ishikawa , Eiichi Kubota , Takehiko Kowatari
IPC分类号： F02M51/00
CPC分类号： F02M51/0671 , F02M51/0685 , F02M2200/07 , F02M2200/304
摘要： In a fuel injection valve used for an internal combustion engine, a valve closing lag time due to fluid resistance in a fuel path is shortened to decrease a minimum injection limit. More specifically, in the fuel injection valve in which an anchor is attracted to an end face part of a stationary core having a fuel path formed at a center part thereof by means of electromagnetic force, and in which a fuel injection hole is opened and closed by controlling a valve disc driven in conjunction with the anchor, there are provided a fuel reservoir part at a center part of an upper end face part of the anchor, a through hole extending axially in a fashion that an end part thereof is open to the fuel reservoir part, and a fuel path extending radially outward from the fuel reservoir part so that fuel is fed to a magnetic attraction gap between an upper end face part of the anchor and a lower end face part of the stationary core. Further, an opening part of a through hole that is open to an upper end face part of the anchor is at least partially opposed to a fuel introduction bore formed in the stationary core, and on the opening part of the through hole, a fuel introduction part is provided for capturing fuel running radially outward from a center side part of the anchor and for guiding the fuel thus captured to the through hole.
摘要翻译：在用于内燃机的燃料喷射阀中，由于燃料路径中的流体阻力引起的关闭滞后时间被缩短以减小最小喷射极限。更具体地说，在燃料喷射阀中，锚具被吸引到具有通过电磁力形成在其中心部分处的燃料路径的固定铁芯的端面部分，并且其中燃料喷射孔被打开和关闭通过控制与锚固件一起驱动的阀盘，在锚固件的上端面部分的中心部分设置有一个燃料储存部分，一个轴向延伸的通孔，该通孔的端部向燃料储存部分和从燃料储存部分径向向外延伸的燃料路径，使得燃料被供给到锚固件的上端面部分和固定铁芯的下端面部分之间的磁吸引间隙。此外，通向孔的上端面部分开口的通孔的开口部分至少部分地与形成在固定铁芯中的燃料导入孔相对，并且在通孔的开口部分上具有燃料引入设置有用于捕获从锚的中心侧径向向外延伸的燃料并且将如此捕获的燃料引导到通孔。

73. 发明授权

US08063679B2 DLL circuit and control method therefor 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US08063679B2
公开(公告)日：2011-11-22
申请号：US12603910
申请日：2009-10-22
申请人： Hiroki Takahashi , Toru Ishikawa
发明人： Hiroki Takahashi , Toru Ishikawa
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/0812
摘要： Jitter is stably reduced. An input clock signal (CLKi) is outputted as an output clock signal (CLKo) via a voltage controlled delay circuit (12), and in addition a delay amount in the voltage controlled delay circuit (12) is controlled based on a result of a phase comparison of the input clock signal (CLKi) and the output clock signal (CLKo). A phase comparison result judging circuit (15) adds up results of phase comparison of the input clock signal (CLKi) and the output clock signal (CLKo) over a prescribed time, and controls the delay amount based on a distribution of addition results.
摘要翻译：抖动稳定减少。通过电压控制延迟电路（12）将输入时钟信号（CLKi）作为输出时钟信号（CLKo）输出，另外根据电压控制延迟电路（12）的结果控制延迟量输入时钟信号（CLKi）和输出时钟信号（CLKo）的相位比较。相位比较结果判断电路（15）在规定时间内将输入时钟信号（CLKi）和输出时钟信号（CLKo）的相位比较结果相加，并根据加法结果的分布来控制延迟量。

74. 发明申请

US20100302874A1 SEMICONDUCTOR MEMORY DEVICE, INFORMATION PROCESSING SYSTEM INCLUDING THE SAME, AND CONTROLLER 有权
标题翻译：半导体存储器件，包括其的信息处理系统和控制器
公开(公告)号：US20100302874A1
公开(公告)日：2010-12-02
申请号：US12784147
申请日：2010-05-20
申请人： Yasushi Takahashi , Toru Ishikawa
发明人： Yasushi Takahashi , Toru Ishikawa
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C11/4096 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093
摘要： To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.
摘要翻译：分别包括分配给第一和第二存储器电路单元的第一和第二数据输入/输出端子以及共同分配给这些存储器电路单元的地址端子。当第一芯片选择信号被激活时，与第二存储器电路单元的操作无关地，第一存储器电路单元基于地址信号经由第一数据输入/输出端执行读操作或写操作。当第二芯片选择信号被激活时，第二存储器电路单元基于地址信号执行经由第二数据输入/输出端子的读取操作或写入操作，而与第一存储器电路单元的操作无关。利用这种配置，可以防止浪费的数据传送，并且可以提高有效的数据传送速率。

75. 发明授权

US07791383B2 Semiconductor device having input circuits activated by clocks having different phases 有权
标题翻译：具有由具有不同相位的时钟激活的输入电路的半导体器件
公开(公告)号：US07791383B2
公开(公告)日：2010-09-07
申请号：US12213817
申请日：2008-06-25
申请人： Toru Ishikawa , Kunihiko Katou
发明人： Toru Ishikawa , Kunihiko Katou
IPC分类号： H03L7/00
CPC分类号： G11C7/1078 , G11C7/1087
摘要： Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD clock signals having different phases are supplied to the respective input circuits. The cycle time of each one input circuit can be made longer by sequentially assigning the serial data supplied to the external input terminals in response to the clock signals having different clock signals. Since the input circuits are isolated from each other by means of the resistor elements, the influence of the kick back signal which occurs at first stage of each the input circuit upon the other input circuit can be made very small.
摘要翻译：响应于提供给其的时钟信号的电平转变以接受输入信号，激活连接到经由电阻元件的外部输入端PAD的输入电路。为了输入施加到外部输入端子的信号，将具有不同相位的时钟信号提供给各个输入电路。通过响应于具有不同时钟信号的时钟信号顺序分配提供给外部输入端的串行数据，可以使每个输入电路的周期时间更长。由于输入电路通过电阻元件彼此隔离，所以可以使在每个输入电路的第一级发生在另一输入电路上的反冲信号的影响非常小。

76. 发明授权

US07759998B2 Timing adjustment circuit 失效
标题翻译：定时调整电路
公开(公告)号：US07759998B2
公开(公告)日：2010-07-20
申请号：US11698892
申请日：2007-01-29
申请人： Toru Ishikawa
发明人： Toru Ishikawa
IPC分类号： H03H11/26
CPC分类号： H03L7/0814 , H03K5/133 , H03K5/135 , H03K5/26 , H03K2005/00071 , H03L7/07 , H03L7/087 , H03L7/091
摘要： Three flip-flops receive a common data signal input through a data terminal based on different timing signals which are obtained from an external timing signal and differ from one another by a specific delay step. A judging circuit judges whether or not the output data of the three flip-flops coincide with one another. If all the output data coincide with one another, the latch timing is maintained, whereas if the output data of the flip-flop latching the data signal at a fastest or latest timing differs from the output data of the flip-flop latching the data signal at the central timing, the judging circuit changes the variable timing to obtain a suitable latch timing.
摘要翻译：三个触发器基于从外部定时信号获得的不同的定时信号，通过数据终端接收公共数据信号，并且通过特定的延迟步骤彼此不同。判断电路判断三个触发器的输出数据是否彼此一致。如果所有输出数据彼此一致，则保持锁存定时，而如果在最快或最新的定时锁存数据信号的触发器的输出数据不同于触发器的输出数据锁存数据信号在中央定时，判断电路改变可变定时以获得合适的锁定定时。

77. 发明授权

US07663956B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07663956B2
公开(公告)日：2010-02-16
申请号：US11952633
申请日：2007-12-07
申请人： Toru Ishikawa
发明人： Toru Ishikawa
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40618
摘要： A semiconductor memory device performs a refresh operation sequentially for a word line selected based on a row address when receiving a refresh request, and comprises: a memory cell array divided into M banks; a refresh counter for sequentially outputting a count value corresponding to the word line to be refreshed in response to the refresh request; and a row address converter for supplying row addresses different from one anther in at lest two banks among the M banks by converting the count value. In the semiconductor memory device, a predetermined number of selected word lines are refreshed at the same time in the banks in accordance with different patterns from one another, and the maximum value of the total number of the selected word lines refreshed at the same time for all the M banks is controlled to be lower than 2M.
摘要翻译：半导体存储器件在接收到刷新请求时，基于行地址选择的字线顺序执行刷新操作，并且包括：划分为M个存储体的存储单元阵列; 刷新计数器，用于响应刷新请求顺序地输出与要刷新的字线对应的计数值; 以及行地址转换器，用于通过转换计数值来提供不同于M组中的至少两个存储体中的一个存储体的行地址的行地址。在半导体存储器件中，根据彼此不同的图案，在存储体中同时刷新预定数量的所选择的字线，同时刷新所选字线的总数的最大值，用于所有M银行都被控制在低于2M。

78. 发明授权

US07620837B2 Data transmission system and data transmission apparatus 失效
公开(公告)号：US07620837B2
公开(公告)日：2009-11-17
申请号：US11890438
申请日：2007-08-06
申请人： Toru Ishikawa
发明人： Toru Ishikawa
IPC分类号： G06F1/12
CPC分类号： G06F13/423 , H04L7/0008
摘要： A data transmission system including a slave device (30) and a master device (10) is disclosed. Slave device (30) may include a slave side clock signal generator section (32) for generating a slave side clock signal (CLKSOUT), a phase adjusting circuit (40) for controlling a phase of a slave side clock signal (CLKSOUT), output sections (33-1 to 33-m) for outputting transmission data signals (SD1 to SDm) in response to slave side clock signal (CLKSOUT), and a timing reference signal generator section (34) for outputting a timing reference signal (SSPH) in response to slave side clock signal (CLKSOUT). Master device (10) may include a master side clock signal generator section (11) for generating master side clock signal (CLKM), input sections (12-1 to 12-m) for sampling data signals (SD1 to SDm) in response to master side clock signal (CLKM), and a phase compare circuit (19) for generating a phase adjustment instruction signal (SADJOUT) based upon timing reference signal (SSPH) and master side clock signal (CLKM). Phase adjusting circuit (40) may adjust a phase of slave side clock signal (CLKSOUT) in response to phase adjustment instruction signal (SADJOUT). In this way, data setup and/or hold times may be improved.

79. 发明申请

US20090088137A1 Highly secured portable telephone system and information system 失效
标题翻译：高度安全的便携式电话系统和信息系统
公开(公告)号：US20090088137A1
公开(公告)日：2009-04-02
申请号：US12219898
申请日：2008-07-30
申请人： Yasuhiko Sasaki , Masashi Yano , Hideo Munehiro , Noriyuki Sugiura , Toru Ishikawa
发明人： Yasuhiko Sasaki , Masashi Yano , Hideo Munehiro , Noriyuki Sugiura , Toru Ishikawa
IPC分类号： H04M1/663
CPC分类号： H04M7/0033 , H04L63/105 , H04M7/003
摘要： In order to solve the problem in that information relating to a specific purpose can be saved in the internal memory of a mobile apparatus on which a permanent memory is mounted while information relating to other purpose cannot be saved in the internal memory of the apparatus, the purpose of each telephone call is distinguished by sending a non-telephone type notice before transferring the call and thus the user can determine whether the call should be saved or not.
摘要翻译：为了解决与特定目的相关的信息可以保存在其上安装有永久存储器的移动装置的内部存储器中，而与其他目的有关的信息不能被保存在装置的内部存储器中的问题，通过在转移呼叫之前发送非电话类型通知来区分每个电话呼叫的目的，因此用户可以确定呼叫是否应该被保存。

80. 发明授权

US07456681B2 Power supply voltage step-down circuit, delay circuit, and semiconductor device having the delay circuit 有权
标题翻译：电源电压降压电路，延迟电路和具有延迟电路的半导体器件
公开(公告)号：US07456681B2
公开(公告)日：2008-11-25
申请号：US11360522
申请日：2006-02-24
申请人： Atsunori Hirobe , Toru Ishikawa
发明人： Atsunori Hirobe , Toru Ishikawa
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/56 , H03K5/133 , H03K2005/00032 , H03K2005/0013
摘要： A delay circuit has a circuit structure dominated by an NMOS or a PMOS transistor. The delay circuit is supplied with, as a power supply voltage, an output voltage of a power supply voltage step-down circuit having a level generating circuit for generating a reference voltage obtained by an offset voltage and a manufacturing variation dependent voltage, and an m-time voltage generating circuit. A semiconductor device includes the delay circuit.
摘要翻译：延迟电路具有由NMOS或PMOS晶体管主导的电路结构。延迟电路具有作为电源电压的电源电压降压电路的输出电压，该电源电压降压电路具有用于产生通过偏移电压和制造变化相关电压获得的参考电压的电平发生电路，并且m 时间电压发生电路。半导体器件包括延迟电路。

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