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1. 发明申请

US20110310681A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110310681A1
公开(公告)日：2011-12-22
申请号：US13164472
申请日：2011-06-20
申请人： Atsunori HIROBE
发明人： Atsunori HIROBE
IPC分类号： G11C7/10
CPC分类号： G11C7/10 , G11C7/1048 , G11C7/22 , G11C11/4076
摘要： A semiconductor device includes a bidirectional first bus arranged in common for a plurality of memory array basic units transferring write data and read data, a second bus transferring address/command, a plurality of first buffer circuits receiving addresses/command transferred to the second bus, wherein a control delay for generating the address/command and preparing write data to the first bus for write access and an output delay for outputting read data are both set to a length greater than or equal to a selection time for writing or reading of data to a memory cell of a selected area.
摘要翻译：一种半导体器件包括：公共布置的用于传送写入数据和读取数据的多个存储器阵列基本单元，第二总线传送地址/命令，接收传送到第二总线的地址/命令的多个第一缓冲器电路的双向第一总线，其中用于产生所述地址/命令的控制延迟以及为所述第一总线准备用于写访问的写入数据和用于输出读取数据的输出延迟都被设置为大于或等于用于写入或读取数据的选择时间的长度所选区域的存储单元。

2. 发明申请

US20110188330A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20110188330A1
公开(公告)日：2011-08-04
申请号：US13014510
申请日：2011-01-26
申请人： Muneaki MATSUSHIGE , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
发明人： Muneaki MATSUSHIGE , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/00 , G11C7/10
摘要： A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.
摘要翻译：半导体存储装置包括：多个存储单元阵列; 多个双向数据总线，与所述多个存储单元阵列中的相应数据总线相对应地设置; 多个双向缓冲电路，其与存储单元阵列相对应地设置，能够连续地连接相邻的双向数据总线，以便中继双向数据总线中的数据; 以及用于控制双向缓冲电路的激活的控制电路。双向缓冲电路被布置为反转逻辑，并且双向缓冲电路被布置成不反转逻辑。

3. 发明授权

US07876637B2 Semiconductor device and memory 有权
标题翻译：半导体器件和存储器
公开(公告)号：US07876637B2
公开(公告)日：2011-01-25
申请号：US11935639
申请日：2007-11-06
申请人： Atsunori Hirobe
发明人： Atsunori Hirobe
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C5/147 , G11C11/4074
摘要： A semiconductor device of the present invention comprises a first step-down voltage circuit to generate a first step-down voltage lower than an externally-supplied power supply voltage, and a second step-down voltage circuit to generate a second step-down voltage lower than the first step-down voltage. The first step-down voltage circuit has a withstand voltage no lower than the power supply voltage and the second step-down voltage circuit has a withstand voltage no lower than the first step-down voltage.
摘要翻译：本发明的半导体器件包括：第一降压电路，用于产生比外部提供的电源电压低的第一降压电压;以及第二降压电路，以产生较低的第二降压电压比第一降压电压。第一降压电路具有不低于电源电压的耐受电压，而第二降压电路具有不低于第一降压电压的耐受电压。

4. 发明授权

US07724588B2 Overdrive write method, write amplifier power generating circuit, and semiconductor memory device including the same 有权
标题翻译：超速写入方法，写入放大器发生电路和包括其的半导体存储器件
公开(公告)号：US07724588B2
公开(公告)日：2010-05-25
申请号：US11671259
申请日：2007-02-05
申请人： Atsunori Hirobe
发明人： Atsunori Hirobe
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/1078 , G11C7/1096 , G11C11/4096
摘要： A write amplifier power generating circuit includes a control unit for changing an output voltage. In a first write cycle in which a pair of bit lines are being amplified, a write operation is performed by an overdrive write method in which a high level from a write amplifier is set to a first voltage (for example, a power supply voltage). In a second write cycle after amplification in the pair of the bit lines has been completed, a write operation is performed by a write method in which the high level from the write amplifier is set to a second voltage (for example, an internal voltage).
摘要翻译：写放大器功率产生电路包括用于改变输出电压的控制单元。在一对位线被放大的第一写入周期中，写入操作是由写入放大器的高电平被设置为第一电压（例如，电源电压）的过驱动写入方法执行的，。在一对位线中的放大之后的第二写入周期已经完成时，通过写入方法执行写入操作，其中写入放大器的高电平被设置为第二电压（例如，内部电压）。

5. 发明申请

US20120287729A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120287729A1
公开(公告)日：2012-11-15
申请号：US13468626
申请日：2012-05-10
申请人： Atsunori HIROBE
发明人： Atsunori HIROBE
IPC分类号： G11C7/10
CPC分类号： G11C11/4093 , G11C7/10 , G11C7/1066 , G11C11/4076 , G11C2207/2272
摘要： A semiconductor device includes a memory cell array including a plurality of memory array basic units, a first bus for transfer of address/control signals, including a first buffer circuit operating as a pipeline register, a second bus for bidirectional transfer of write/read data, including a second buffer circuit operating as a pipeline register, a first control circuit sequentially sending the address/control signals on the first bus, and a second control circuit sequentially sending/receiving write/read data on the second bus (FIG. 11).
摘要翻译：半导体器件包括存储单元阵列，该存储单元阵列包括多个存储器阵列基本单元，用于传送地址/控制信号的第一总线，包括作为流水线寄存器工作的第一缓冲器电路，用于双向传送写/读数据的第二总线，包括作为流水线寄存器工作的第二缓冲电路，第一控制电路在第一总线上顺序发送地址/控制信号，以及第二控制电路，在第二总线上顺序地发送/接收写入/读取数据（图11）。

6. 发明授权

US07839205B2 Step-down circuit, semiconductor device, and step-down circuit controlling method 失效
标题翻译：降压电路，半导体器件和降压电路控制方法
公开(公告)号：US07839205B2
公开(公告)日：2010-11-23
申请号：US12314489
申请日：2008-12-11
申请人： Atsunori Hirobe
发明人： Atsunori Hirobe
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C11/4074 , G11C2207/2227
摘要： A step-down circuit is connected between a power supply node for supplying a supply voltage and an internal power supply line for supplying a power to the object circuit and steps-down the supply voltage, and supplies the stepped-down voltage to the object circuit through the internal power supply line. The step-down circuit includes a comparison circuit that compares a reference voltage with the voltage of the internal power supply line, and a driver that adjusts a current flowing between the internal power supply line and the power supply node according to the comparison result of the comparison circuit. The activity level of the driver is controlled so as to rise in a predetermined rising period synchronously with an activated operation of the object circuit and to fall in a predetermined falling period that comes after the rising period.
摘要翻译：降压电路连接在用于提供电源电压的电源节点和用于向目标电路供电的内部电源线和降低电源电压之间，并且将降压电压提供给对象电路通过内部电源线。降压电路包括：比较电路，其将参考电压与内部电源线的电压进行比较;以及驱动器，其根据所述内部电源线的比较结果调整在所述内部电源线和所述电源节点之间流动的电流比较电路。驱动器的活动电平被控制为与目标电路的激活操作同步地上升到预定的上升周期，并且下降到在上升周期之后的预定下降周期。

7. 发明申请

US20090167421A1 Step-down circuit, semiconductor device, and step-down circuit controlling method 失效
标题翻译：降压电路，半导体器件和降压电路控制方法
公开(公告)号：US20090167421A1
公开(公告)日：2009-07-02
申请号：US12314489
申请日：2008-12-11
申请人： Atsunori Hirobe
发明人： Atsunori Hirobe
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C11/4074 , G11C2207/2227
摘要： A step-down circuit is connected between a power supply node for supplying a supply voltage and an internal power supply line for supplying a power to the object circuit and steps-down the supply voltage, and supplies the stepped-down voltage to the object circuit through the internal power supply line. The step-down circuit includes a comparison circuit that compares a reference voltage with the voltage of the internal power supply line, and a driver that adjusts a current flowing between the internal power supply line and the power supply node according to the comparison result of the comparison circuit. The activity level of the driver is controlled so as to rise in a predetermined rising period synchronously with an activated operation of the object circuit and to fall in a predetermined falling period that comes after the rising period.
摘要翻译：降压电路连接在用于提供电源电压的电源节点和用于向目标电路供电的内部电源线和降低电源电压之间，并且将降压电压提供给对象电路通过内部电源线。降压电路包括：比较电路，其将参考电压与内部电源线的电压进行比较;以及驱动器，其根据所述内部电源线的比较结果调整在所述内部电源线和所述电源节点之间流动的电流比较电路。驱动器的活动电平被控制为与目标电路的激活操作同步地上升到预定的上升周期，并且下降到在上升周期之后的预定下降周期。

8. 发明授权

US07436732B2 Internal power supply generating circuit without a dead band 有权
标题翻译：内部电源发生电路没有死区
公开(公告)号：US07436732B2
公开(公告)日：2008-10-14
申请号：US11671937
申请日：2007-02-06
申请人： Atsunori Hirobe
发明人： Atsunori Hirobe
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： An internal power supply generating circuit has a control circuit for controlling a control node voltage of a driver circuit thereof. During an overdrive duration, the control node voltage is set at an appropriate level of an operation range by controlling the control node voltage by the control circuit. By setting the control node voltage at the appropriate level, the internal power supply generating circuit can supply an internal power-supply voltage without a dead band after the overdrive duration. With this structure, the internal power supply generating circuit without the dead band can be obtained and a semiconductor device operable at a high speed comprising the internal power supply generating circuit can be obtained.
摘要翻译：内部电源产生电路具有用于控制其驱动电路的控制节点电压的控制电路。在过驱动持续时间期间，通过控制电路控制控制节点电压，将控制节点电压设置在操作范围的适当水平。通过将控制节点电压设定在适当的电平，内部电源发生电路能够在过驱动持续时间之后提供没有死区的内部电源电压。利用这种结构，可以获得没有死区的内部电源产生电路，并且可以获得包括内部电源产生电路的高速运行的半导体器件。

9. 发明申请

US20070008793A1 Semiconductor apparatus 审中-公开
标题翻译：半导体装置
公开(公告)号：US20070008793A1
公开(公告)日：2007-01-11
申请号：US11481184
申请日：2006-07-06
申请人： Atsunori Hirobe
发明人： Atsunori Hirobe
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/08 , G11C11/4074 , G11C11/4076
摘要： Disclosed is an apparatus for detecting power supply dependency and process dependency of a delay circuit to enable control of the delay of the delay circuit and operation acceleration/deceleration. The apparatus includes a first delay circuit receiving a first signal and delaying the first signal received by a preset delay time to output the so delayed signal, a second delay circuit receiving the first signal in common with the first delay circuit and outputting signals of different delay amounts from plural output ends thereof, and a plural number of comparator circuits provided in association with the plural outputs of the second delay circuit, each configured to receive an output of the first delay circuit and a corresponding output of the second delay circuit and to compare the signals received. The delay of the control signal is varied by a variable delay circuit, based on plural outputs of the plural comparator circuits, in order to variably control e.g. the operation timing of a circuit being controlled.
摘要翻译：公开了一种用于检测延迟电路的电源依赖性和处理依赖性的装置，以便能够控制延迟电路的延迟和操作加速/减速。该装置包括：第一延迟电路，接收第一信号并延迟由预设的延迟时间接收的第一信号，以输出如此延迟的信号;第二延迟电路，与第一延迟电路共同接收第一信号，并输出不同延迟的信号多个输出端的数量以及与第二延迟电路的多个输出相关联地设置的多个比较器电路，每个被配置为接收第一延迟电路的输出和第二延迟电路的相应输出，并进行比较收到的信号。基于多个比较器电路的多个输出，控制信号的延迟由可变延迟电路改变，以便可变地控制例如电路的操作定时被控制。

10. 发明申请

US20060192610A1 Power supply voltage step-down circuit, delay circuit, and semiconductor device having the delay circuit 有权
标题翻译：电源电压降压电路，延迟电路和具有延迟电路的半导体器件
公开(公告)号：US20060192610A1
公开(公告)日：2006-08-31
申请号：US11360522
申请日：2006-02-24
申请人： Atsunori Hirobe , Toru Ishikawa
发明人： Atsunori Hirobe , Toru Ishikawa
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , H03K5/133 , H03K2005/00032 , H03K2005/0013
摘要： A delay circuit has a circuit structure dominated by an NMOS or a PMOS transistor. The delay circuit is supplied with, as a power supply voltage, an output voltage of a power supply voltage step-down circuit having a level generating circuit for generating a reference voltage obtained by an offset voltage and a manufacturing variation dependent voltage, and an m-time voltage generating circuit. A semiconductor device includes the delay circuit.
摘要翻译：延迟电路具有由NMOS或PMOS晶体管主导的电路结构。延迟电路具有作为电源电压的电源电压降压电路的输出电压，该电源电压降压电路具有用于产生通过偏移电压和制造变化相关电压获得的参考电压的电平发生电路，并且m 时间电压发生电路。半导体器件包括延迟电路。

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