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1. 发明授权

US08035432B2 DLL circuit and control method thereof 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US08035432B2
公开(公告)日：2011-10-11
申请号：US12603850
申请日：2009-10-22
申请人： Hiroki Takahashi , Toru Ishikawa
发明人： Hiroki Takahashi , Toru Ishikawa
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/087
摘要： A DLL circuit includes a first phase comparing circuit that compares phases between an input clock signal and an output clock signal, a first delay circuit that delays the output clock signal, and a second phase comparing circuit that compares phases between the input clock signal and an output signal of the first delay circuit. A delay amount in the variable delay circuit is controlled based on a comparison result of the first phase comparing circuit and a comparison result of the second phase comparing circuit.
摘要翻译： DLL电路包括：第一相位比较电路，其比较输入时钟信号和输出时钟信号之间的相位，延迟输出时钟信号的第一延迟电路;以及第二相位比较电路，其比较输入时钟信号和第一延迟电路的输出信号。基于第一相位比较电路的比较结果和第二相位比较电路的比较结果来控制可变延迟电路中的延迟量。

2. 发明申请

US20100123499A1 INFORMATION SYSTEM, SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR 审中-公开
标题翻译：信息系统，半导体器件及其控制方法
公开(公告)号：US20100123499A1
公开(公告)日：2010-05-20
申请号：US12619396
申请日：2009-11-16
申请人： Hiroki TAKAHASHI , Toru Ishikawa
发明人： Hiroki TAKAHASHI , Toru Ishikawa
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , H03L7/095
摘要： An information system with an enhanced effect in reducing jitter with a short period. An input clock signal CLKi is output via a voltage-controlled delay circuit 14 as an output clock signal CLKo, and an amount of delay in the voltage-controlled delay circuit 14 is controlled based on the result of comparison of a phase of the input clock signal CLKi and that of the output clock signal CLKo. A phase correction circuit 21 receives the input clock signal CLKi and the output clock signal CLKo. If, after the DLL circuit has become locked, the input clock signal and the output clock signal are out of phase relative to each other, the phase correction circuit 21 corrects the phase of the input clock signal CLKi based on a phase of the output clock signal CLKo to output a signal to the variable delay circuit 14 (FIG. 1).
摘要翻译：一种在短时间内减少抖动的增强效果的信息系统。输入时钟信号CLKi经由电压控制延迟电路14输出作为输出时钟信号CLKo，并且基于输入时钟的相位比较的结果来控制压控延迟电路14的延迟量信号CLKi和输出时钟信号CLKo的信号。相位校正电路21接收输入时钟信号CLKi和输出时钟信号CLKo。如果在DLL电路被锁定之后，输入时钟信号和输出时钟信号彼此相位不相位，则相位校正电路21基于输出时钟的相位校正输入时钟信号CLKi的相位信号CLKo将信号输出到可变延迟电路14（图1）。

3. 发明申请

US20100102862A1 DLL CIRCUIT AND CONTROL METHOD THEREFOR 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US20100102862A1
公开(公告)日：2010-04-29
申请号：US12603910
申请日：2009-10-22
申请人： Hiroki TAKAHASHI , Toru Ishikawa
发明人： Hiroki TAKAHASHI , Toru Ishikawa
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/0812
摘要： Jitter is stably reduced. An input clock signal (CLKi) is outputted as an output clock signal (CLKo) via a voltage controlled delay circuit (12), and in addition a delay amount in the voltage controlled delay circuit (12) is controlled based on a result of a phase comparison of the input clock signal (CLKi) and the output clock signal (CLKo). A phase comparison result judging circuit (15) adds up results of phase comparison of the input clock signal (CLKi) and the output clock signal (CLKo) over a prescribed time, and controls the delay amount based on a distribution of addition results.
摘要翻译：抖动稳定减少。通过电压控制延迟电路（12）将输入时钟信号（CLKi）作为输出时钟信号（CLKo）输出，另外根据电压控制延迟电路（12）的结果控制延迟量输入时钟信号（CLKi）和输出时钟信号（CLKo）的相位比较。相位比较结果判断电路（15）在规定时间内将输入时钟信号（CLKi）和输出时钟信号（CLKo）的相位比较结果相加，并根据加法结果的分布来控制延迟量。

4. 发明授权

US08063679B2 DLL circuit and control method therefor 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US08063679B2
公开(公告)日：2011-11-22
申请号：US12603910
申请日：2009-10-22
申请人： Hiroki Takahashi , Toru Ishikawa
发明人： Hiroki Takahashi , Toru Ishikawa
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/0812
摘要： Jitter is stably reduced. An input clock signal (CLKi) is outputted as an output clock signal (CLKo) via a voltage controlled delay circuit (12), and in addition a delay amount in the voltage controlled delay circuit (12) is controlled based on a result of a phase comparison of the input clock signal (CLKi) and the output clock signal (CLKo). A phase comparison result judging circuit (15) adds up results of phase comparison of the input clock signal (CLKi) and the output clock signal (CLKo) over a prescribed time, and controls the delay amount based on a distribution of addition results.
摘要翻译：抖动稳定减少。通过电压控制延迟电路（12）将输入时钟信号（CLKi）作为输出时钟信号（CLKo）输出，另外根据电压控制延迟电路（12）的结果控制延迟量输入时钟信号（CLKi）和输出时钟信号（CLKo）的相位比较。相位比较结果判断电路（15）在规定时间内将输入时钟信号（CLKi）和输出时钟信号（CLKo）的相位比较结果相加，并根据加法结果的分布来控制延迟量。

5. 发明授权

US08953409B2 Semiconductor device capable of minimizing mutual effects between two different operations therein 有权
标题翻译：能够最小化其中两种不同操作之间的相互影响的半导体器件
公开(公告)号：US08953409B2
公开(公告)日：2015-02-10
申请号：US12929965
申请日：2011-02-28
申请人： Toru Ishikawa
发明人： Toru Ishikawa
IPC分类号： G11C8/18 , G11C7/00
CPC分类号： G11C11/406 , G11C7/00
摘要： A device includes a control circuit that triggers a first operation every time a specific signal is supplied thereto, and that triggers a second operation in place of the first operation in response to the first specific signal supplied after the number of the first operation performed has reached a predetermined number.
摘要翻译：一种设备包括控制电路，每当向其提供特定信号时触发第一操作，并且响应于在执行的第一操作的数量已经达到之后提供的第一特定信号，触发第二操作代替第一操作预定数量。

6. 发明授权

US08654557B2 Semiconductor memory device, information processing system including the same, and controller 有权
标题翻译：半导体存储器件，包括其的信息处理系统和控制器
公开(公告)号：US08654557B2
公开(公告)日：2014-02-18
申请号：US13593046
申请日：2012-08-23
申请人： Yasushi Takahashi , Toru Ishikawa
发明人： Yasushi Takahashi , Toru Ishikawa
IPC分类号： G11C5/06
CPC分类号： G11C11/4096 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093
摘要： A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the semiconductor substrate and electrically coupled to the first and second selection signal terminals of the controller, respectively. Multiple third data terminals are provided on the semiconductor substrate and electrically coupled to the first data terminals of the controller, respectively. Multiple fourth data terminals are provided on the semiconductor substrate and electrically coupled to the second data terminals of the controller, respectively. The first and third data terminals communicate first data in response to the first selection signal. The second and fourth data terminals communicate second data in response to the second selection signal.
摘要翻译：一种包括控制器和存储器芯片的系统。控制器包括分别提供第一和第二选择信号的第一和第二选择信号端，多个第一数据终端和多个第二数据终端。存储器芯片包括半导体衬底，设置在半导体衬底上并分别电耦合到控制器的第一和第二选择信号端子的第三和第四选择信号端子。多个第三数据端子分别设置在半导体衬底上并电连接到控制器的第一数据端。多个第四数据端子分别设置在半导体衬底上并电连接到控制器的第二数据端。第一和第三数据终端响应于第一选择信号来传送第一数据。第二和第四数据终端响应于第二选择信号传送第二数据。

7. 发明申请

US20140017574A1 ADDITIVE FOR SODIUM ION SECONDARY BATTERY AND SODIUM ION SECONDARY BATTERY 有权
标题翻译：用于钠离子二次电池和钠离子二次电池的添加剂
公开(公告)号：US20140017574A1
公开(公告)日：2014-01-16
申请号：US14007250
申请日：2012-03-08
申请人： Atsushi Ito , Yasuhiko Ohsawa , Shinichi Komaba , Naoaki Yabuuchi , Wataru Murata , Toru Ishikawa , Yuta Matsuura
发明人： Atsushi Ito , Yasuhiko Ohsawa , Shinichi Komaba , Naoaki Yabuuchi , Wataru Murata , Toru Ishikawa , Yuta Matsuura
IPC分类号： H01M10/0567 , H01M10/054
CPC分类号： H01M10/0567 , H01M4/366 , H01M4/587 , H01M10/054 , H01M2300/0025
摘要： An additive for a sodium ion secondary battery of the present invention includes a compound of at least one of a saturated cyclic carbonate having a fluoro group and a chain carbonate having a fluoro group. A sodium ion secondary battery (1) of the present invention includes: a non-aqueous electrolytic solution including the additive for a sodium ion secondary battery and a non-aqueous solvent containing a saturated cyclic carbonate or a non-aqueous solvent containing a saturated cyclic carbonate and a chain carbonate; a positive electrode (11); and a negative electrode (12) that includes a coating formed in a surface of the negative electrode, the coating containing a composite material having carbon, oxygen, fluorine and sodium in the surface and includes a negative-electrode active material containing a hard carbon.
摘要翻译：本发明的钠离子二次电池用添加剂包括具有氟基的饱和环状碳酸酯和具有氟基的链状碳酸酯中的至少一种的化合物。本发明的钠离子二次电池（1）包括：含有钠离子二次电池用添加剂和含有饱和环状碳酸酯或含有饱和环状碳酸酯的非水溶剂的非水溶剂的非水电解液碳酸酯和链状碳酸酯; 正极（11）; 和包含在负极表面形成的涂层的负极（12），所述涂层含有表面上具有碳，氧，氟和钠的复合材料，并且包括含有硬碳的负极活性物质。

8. 发明申请

US20120263003A1 DEVICE PERFORMING REFRESH OPERATIONS OF MEMORY AREAS 有权
标题翻译：执行存储区刷新操作的设备
公开(公告)号：US20120263003A1
公开(公告)日：2012-10-18
申请号：US13444032
申请日：2012-04-11
申请人： Kenichi SAKAKIBARA , Toru Ishikawa
发明人： Kenichi SAKAKIBARA , Toru Ishikawa
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C11/40618
摘要： Disclosed herein is a device that includes a plurality of memory circuits and a refresh control circuit configured to generate a plurality of refresh initiation signals such that one of the refresh initiation signals takes an active level. Each of the memory circuits comprises a memory cell array including a plurality of memory cells, at least one data terminal, a data read/write circuit performing a data read operation to read out read-data from a selected one of the memory cells and supply the read-data to the data terminal and a data write operation to receive write-data from the data terminal and write the write-data into a selected one of the memory cells, and a refresh circuit performing a data refresh operation on selected one or ones of the memory cells of the memory cell array in response to an associated one of the refresh initiation signals taking the active level.
摘要翻译：本文公开了一种包括多个存储器电路和刷新控制电路的装置，该刷新控制电路被配置为产生多个刷新启动信号，使得刷新启动信号中的一个获得有效电平。每个存储器电路包括存储单元阵列，该存储单元阵列包括多个存储单元，至少一个数据端，数据读/写电路，执行数据读操作，以从所选存储单元中读出读数据并提供读取数据到数据终端，以及数据写入操作，以从数据终端接收写入数据，并将写入数据写入所选择的一个存储器单元;以及刷新电路，对选择的一个或所述存储器单元阵列的存储单元中的一个响应于所述刷新启动信号中的相关联的一个采用有效电平。

9. 发明授权

US08274844B2 Semiconductor memory device, information processing system including the same, and controller 有权
标题翻译：半导体存储器件，包括其的信息处理系统和控制器
公开(公告)号：US08274844B2
公开(公告)日：2012-09-25
申请号：US12784147
申请日：2010-05-20
申请人： Yasushi Takahashi , Toru Ishikawa
发明人： Yasushi Takahashi , Toru Ishikawa
IPC分类号： G11C7/00
CPC分类号： G11C11/4096 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093
摘要： To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.
摘要翻译：分别包括分配给第一和第二存储器电路单元的第一和第二数据输入/输出端子以及共同分配给这些存储器电路单元的地址端子。当第一芯片选择信号被激活时，与第二存储器电路单元的操作无关地，第一存储器电路单元基于地址信号经由第一数据输入/输出端执行读操作或写操作。当第二芯片选择信号被激活时，第二存储器电路单元基于地址信号执行经由第二数据输入/输出端子的读取操作或写入操作，而与第一存储器电路单元的操作无关。利用这种配置，可以防止浪费的数据传送，并且可以提高有效的数据传送速率。

10. 发明申请

US20110216612A1 Device 有权
标题翻译：设备
公开(公告)号：US20110216612A1
公开(公告)日：2011-09-08
申请号：US12929965
申请日：2011-02-28
申请人： Toru Ishikawa
发明人： Toru Ishikawa
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/00
摘要： A device includes a control circuit that triggers a first operation every time a specific signal is supplied thereto, and that triggers a second operation in place of the first operation in response to the first specific signal supplied after the number of the first operation performed has reached a predetermined number.
摘要翻译：一种设备包括控制电路，每当向其提供特定信号时触发第一操作，并且响应于在执行的第一操作的数量已经达到之后提供的第一特定信号，触发第二操作代替第一操作预定数量。

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