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1. 发明申请

US20080265956A1 Semiconductor device having input circuits activated by clocks having different phases 有权
公开(公告)号：US20080265956A1
公开(公告)日：2008-10-30
申请号：US12213817
申请日：2008-06-25
申请人： Toru Ishikawa , Kunihiko Katou
发明人： Toru Ishikawa , Kunihiko Katou
IPC分类号： H03L7/00
CPC分类号： G11C7/1078 , G11C7/1087
摘要： Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD clock signals having different phases are supplied to the respective input circuits. The cycle time of each one input circuit can be made longer by sequentially assigning the serial data supplied to the external input terminals in response to the clock signals having different clock signals. Since the input circuits are isolated from each other by means of the resistor elements, the influence of the kick back signal which occurs at first stage of each the input circuit upon the other input circuit can be made very small.

2. 发明申请

US20060125541A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060125541A1
公开(公告)日：2006-06-15
申请号：US11296287
申请日：2005-12-08
申请人： Toru Ishikawa , Kunihiko Katou
发明人： Toru Ishikawa , Kunihiko Katou
IPC分类号： G06F1/04
CPC分类号： G11C7/1078 , G11C7/1087
摘要： To stably operate a semiconductor device comprising a plurality of input circuits which are connected to one external input terminal. Input circuits 10, 11, 12, 13 connected to an external input terminal PAD via resistor elements R1, R2, R3, R4, respectively, are activated in response to the level transition of the clock signals CK10, CK11, CK12, CK13 supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD clock signals having different phases are supplied to the respective input circuits. The cycle time of each one input circuit can be made longer by sequentially assigning the serial data supplied to the external input terminals in response to the clock signals having different clock signals. Since the input circuits are isolated from each other by means of the resistor elements R1, R2, R3, R4, the influence of the kick back signal which occurs at first stage of each the input circuit upon the other input circuit can be made very small.
摘要翻译：为了稳定地操作包括连接到一个外部输入端子的多个输入电路的半导体器件。分别经由电阻元件R 1，R 2，R 3，R 4连接到外部输入端子PAD的输入电路10,11,12,13响应于时钟信号CK10，CK11的电平转换而被激活，CK12，CK13，供接收输入信号。为了输入施加到外部输入端子的信号，将具有不同相位的时钟信号提供给各个输入电路。通过响应于具有不同时钟信号的时钟信号顺序分配提供给外部输入端的串行数据，可以使每个输入电路的周期时间更长。由于输入电路通过电阻元件R 1，R 2，R 3，R 4彼此隔离，所以在每个输入电路的第一级发生的反冲信号对另一输入电路的影响可以做得很小

3. 发明授权

US07400180B2 Semiconductor device having input circuits activated by clocks having different phases 失效
标题翻译：具有由具有不同相位的时钟激活的输入电路的半导体器件
公开(公告)号：US07400180B2
公开(公告)日：2008-07-15
申请号：US11296287
申请日：2005-12-08
申请人： Toru Ishikawa , Kunihiko Katou
发明人： Toru Ishikawa , Kunihiko Katou
IPC分类号： H03L7/00
CPC分类号： G11C7/1078 , G11C7/1087
摘要： Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD clock signals having different phases are supplied to the respective input circuits. The cycle time of each one input circuit can be made longer by sequentially assigning the serial data supplied to the external input terminals in response to the clock signals having different clock signals. Since the input circuits are isolated from each other by means of the resistor elements, the influence of the kick back signal which occurs at first stage of each the input circuit upon the other input circuit can be made very small.
摘要翻译：响应于提供给其的时钟信号的电平转变以接受输入信号，激活连接到经由电阻元件的外部输入端PAD的输入电路。为了输入施加到外部输入端子的信号，将具有不同相位的时钟信号提供给各个输入电路。通过响应于具有不同时钟信号的时钟信号顺序分配提供给外部输入端的串行数据，可以使每个输入电路的周期时间更长。由于输入电路通过电阻元件彼此隔离，所以可以使在每个输入电路的第一级发生在另一输入电路上的反冲信号的影响非常小。

4. 发明授权

US06191045B1 Method of treating surface of sample 有权
标题翻译：处理样品表面的方法
公开(公告)号：US06191045B1
公开(公告)日：2001-02-20
申请号：US09302438
申请日：1999-04-30
申请人： Motohiko Yoshigai , Hiroshi Hasegawa , Hiroshi Akiyama , Takafumi Tokunaga , Tadashi Umezawa , Masayuki Kojima , Kazuo Nojiri , Hiroshi Kawakami , Kunihiko Katou
发明人： Motohiko Yoshigai , Hiroshi Hasegawa , Hiroshi Akiyama , Takafumi Tokunaga , Tadashi Umezawa , Masayuki Kojima , Kazuo Nojiri , Hiroshi Kawakami , Kunihiko Katou
IPC分类号： H01L2100
CPC分类号： H01L21/67069 , H01L21/32136 , H01L21/32137
摘要： In order to provide a method of treating a multilayer including metal and polysilicon for use in a conductor or a gate electrode of a semiconductor device with high accuracy at a high selectivity, the temperature of a sample is maintained at 100° C. or higher at the time of etching a metal film to increase the etch rate of the metal film. In order to suppress the etch rate of a polysilicon film and prevent side etching, an oxygen gas is added to a gas containing a halogen element. In order to suppress the etch rate of a silicon oxide film at the time of etching the polysilicon film, the etching is performed with etch parameters which are divided into those for the metal film and those for the polysilicon film. In the etching performed to the multilayer containing metal and polysilicon, by etching the metal film at a high temperature of 100° C. or higher, the etch rate of the metal film becomes high. Consequently, there is no partial etch residue of the metal film and a barrier film. By switching the parameters to those with which the polysilicon film can be etched at a high selectivity with respect to an oxide film at the time point of completion of etching to the barrier film, very accurate treatment can be realized.
摘要翻译：为了提供以高选择性以高精度处理用于半导体器件的导体或栅电极的金属和多晶硅的多层的方法，将样品的温度保持在100℃以上蚀刻金属膜以增加金属膜的蚀刻速率的时间。为了抑制多晶硅膜的蚀刻速度并防止侧面蚀刻，将氧气添加到含有卤素元素的气体中。为了抑制蚀刻多晶硅膜时的氧化硅膜的蚀刻速率，用蚀刻参数进行蚀刻，蚀刻参数分为金属膜和多晶硅膜蚀刻参数。在对多层容纳金属和多晶硅进行的蚀刻中，通过在100℃以上的高温下蚀刻金属膜，金属膜的蚀刻速度变高。因此，不存在金属膜和阻挡膜的部分蚀刻残留。通过在对阻挡膜的蚀刻完成时刻将参数切换为能够以相对于氧化膜的高选择性蚀刻多晶硅膜的参数，可以实现非常精确的处理。

5. 发明授权

US07791383B2 Semiconductor device having input circuits activated by clocks having different phases 有权
标题翻译：具有由具有不同相位的时钟激活的输入电路的半导体器件
公开(公告)号：US07791383B2
公开(公告)日：2010-09-07
申请号：US12213817
申请日：2008-06-25
申请人： Toru Ishikawa , Kunihiko Katou
发明人： Toru Ishikawa , Kunihiko Katou
IPC分类号： H03L7/00
CPC分类号： G11C7/1078 , G11C7/1087
摘要： Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD clock signals having different phases are supplied to the respective input circuits. The cycle time of each one input circuit can be made longer by sequentially assigning the serial data supplied to the external input terminals in response to the clock signals having different clock signals. Since the input circuits are isolated from each other by means of the resistor elements, the influence of the kick back signal which occurs at first stage of each the input circuit upon the other input circuit can be made very small.
摘要翻译：响应于提供给其的时钟信号的电平转变以接受输入信号，激活连接到经由电阻元件的外部输入端PAD的输入电路。为了输入施加到外部输入端子的信号，将具有不同相位的时钟信号提供给各个输入电路。通过响应于具有不同时钟信号的时钟信号顺序分配提供给外部输入端的串行数据，可以使每个输入电路的周期时间更长。由于输入电路通过电阻元件彼此隔离，所以可以使在每个输入电路的第一级发生在另一输入电路上的反冲信号的影响非常小。

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