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71. 发明申请

US20100077372A1 Apparatus, Method and Computer Program Product for Fast Stimulation of Manufacturing Effects During Integrated Circuit Design 有权
标题翻译：集成电路设计中快速刺激制造效果的装置，方法和计算机程序产品
公开(公告)号：US20100077372A1
公开(公告)日：2010-03-25
申请号：US12237727
申请日：2008-09-25
申请人： Hua Xiang , Laertis Economikos , Mohammed F. Fayaz , Stephen E. Greco , Patricia A. O'Neil , Ruchir Puri
发明人： Hua Xiang , Laertis Economikos , Mohammed F. Fayaz , Stephen E. Greco , Patricia A. O'Neil , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/12 , Y02P90/265
摘要： Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.
摘要翻译：方法，设备和计算机程序产品提供了一种快速准确的模型，用于通过生成集成电路的设计来模拟集成电路制造过程中的化学机械抛光（CMP）步骤的影响; 同时产生集成电路的设计，使用简化模型来预测由在集成电路的制造期间使用的CMP处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从执行的模拟导出的之前的设计生成活动使用综合仿真程序来模拟物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。

72. 发明授权

US07354333B2 Detection of diamond contamination in polishing pad 有权
标题翻译：检测抛光垫中的金刚石污染
公开(公告)号：US07354333B2
公开(公告)日：2008-04-08
申请号：US10905816
申请日：2005-01-21
申请人： Laertis Economikos , John A. Fitzsimmons
发明人： Laertis Economikos , John A. Fitzsimmons
IPC分类号： B24B49/00 , B24B51/00
CPC分类号： B24B53/017
摘要： Methods for reconditioning a polishing pad and detecting diamond contamination of the polishing pad, are disclosed. In particular, the methods include the step of exposing the reconditioned polishing pad to an energy source to induce the diamond contamination to fluoresce. Detection of the diamond contamination is then made by detecting the fluorescence. Removal of the diamond contamination results in an improved reconditioned polishing pad. A reconditioning system for reconditioning a damaged polishing pad is also disclosed. The reconditioning system includes a reconditioning disk including a plurality of diamonds for reconditioning the polishing pad, wherein each diamond fluoresces when exposed to an energy source.
摘要翻译：公开了用于修复抛光垫并检测抛光垫的金刚石污染的方法。特别地，所述方法包括将修复后的抛光垫暴露于能量源以引起金刚石污染物发荧光的步骤。然后通过检测荧光来检测金刚石污染物。去除金刚石污染导致改进的修复抛光垫。还公开了一种用于修复损坏的抛光垫的修复系统。修复系统包括修复盘，其包括用于修复抛光垫的多个金刚石，其中当暴露于能量源时，每个金刚石发荧光。

73. 发明授权

US07214623B2 Planarization system and method using a carbonate containing fluid 失效
标题翻译：使用含碳酸盐的流体的平面化系统和方法
公开(公告)号：US07214623B2
公开(公告)日：2007-05-08
申请号：US10605610
申请日：2003-10-13
申请人： Donald J. Delehanty , James W. Hannah , Daniel M. Heenan , Fen F. Jamin , Laertis Economikos
发明人： Donald J. Delehanty , James W. Hannah , Daniel M. Heenan , Fen F. Jamin , Laertis Economikos
IPC分类号： H01L21/302
CPC分类号： C09G1/04 , B24B7/228 , H01L21/31053
摘要： Disclosed herein are a system and method of polishing a layer of a substrate. The disclosed method includes providing a polishing apparatus adapted to impart relative movement between a polishing pad and a substrate having a first layer to be polished; providing a liquid medium having a pH between 4 and 11 to an interface between the substrate and the polishing pad, the liquid medium including a pH controlling substance including at least one of an acid and a base, a carbonate and a stabilizer additive comprising at least one selected from the group consisting of amino acids and polyacrylic acid; and moving at least one of the substrate and the polishing pad relative to the other to polish the layer of the substrate.
摘要翻译：本文公开了一种抛光衬底层的系统和方法。所公开的方法包括提供适于在抛光垫和具有要抛光的第一层的基底之间施加相对运动的抛光装置; 提供pH在4和11之间的液体介质到基底和抛光垫之间的界面，液体介质包括pH控制物质，其包括酸和碱中的至少一种，碳酸盐和稳定剂添加剂，至少包括一个选自氨基酸和聚丙烯酸; 并且相对于另一个移动衬底和抛光垫中的至少一个以抛光衬底的层。

74. 发明授权

US07091103B2 TEOS assisted oxide CMP process 失效
标题翻译： TEOS辅助氧化物CMP工艺
公开(公告)号：US07091103B2
公开(公告)日：2006-08-15
申请号：US10314865
申请日：2002-12-09
申请人： Jochen Beintner , Laertis Economikos , Michael Wise , Andreas Knorr
发明人： Jochen Beintner , Laertis Economikos , Michael Wise , Andreas Knorr
IPC分类号： H01L21/76 , H01L21/461 , H01L21/302
CPC分类号： H01L21/76819 , H01L21/31053 , H01L21/31055 , H01L27/1087 , H01L27/10894
摘要： CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.
摘要翻译：包含具有沟槽电容器的DRAM阵列的集成电路的CMP用氧化物填充沟槽，导致与周围的支撑结构中的浓度相比密集的氧化物结构的阵列，因此具有更高的负载。保形层沉积在晶片上，增加阵列中的负载，但填充有效区域之间的空间。覆盖蚀刻去除阵列和支撑体中的材料。块蚀刻平衡阵列中的材料和支撑体的数量。阵列中的补充氧化物沉积将结构之间的空间填充到几乎均匀的密度。

75. 发明申请

US20050179112A1 Filling high aspect ratio isolation structures with polysilazane based material 审中-公开
标题翻译：用聚硅氮烷基材料填充高纵横比隔离结构
公开(公告)号：US20050179112A1
公开(公告)日：2005-08-18
申请号：US11035392
申请日：2005-01-12
申请人： Michael Belyansky , Rama Divakaruni , Laertis Economikos , Rajarao Jammy , Kenneth Settlemyer , Padraic Shafer
发明人： Michael Belyansky , Rama Divakaruni , Laertis Economikos , Rajarao Jammy , Kenneth Settlemyer , Padraic Shafer
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76229
摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H20 ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.
摘要翻译：包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率通过HDP技术，并且耐用性足以承受CMP抛光。

76. 发明申请

US20050170661A1 Method of forming a trench structure 审中-公开
标题翻译：形成沟槽结构的方法
公开(公告)号：US20050170661A1
公开(公告)日：2005-08-04
申请号：US10708035
申请日：2004-02-04
申请人： Laertis Economikos , Klaus Hummler
发明人： Laertis Economikos , Klaus Hummler
IPC分类号： H01L21/31 , H01L21/762 , H01L21/768
CPC分类号： H01L21/76229 , H01L21/7684
摘要： A method of fabricating a filled trench structure, the method including: (a) forming a first set of trenches in a first region of a substrate and forming a second set of trenches in a second region of the substrate, trenches in the first set of trenches having a higher aspect ratio than the trenches in the second region; (b) depositing a fill material in the first and second set of trenches and on a top surface of the substrate, the fill material completely filling the trenches; (c) removing an upper portion of the fill material; and (d) removing, using a planarization process, all fill material from the top surface of the substrate, a top surface of the fill material in the first and second sets of trenches co-planer with the top surface of the substrate.
摘要翻译：一种制造填充沟槽结构的方法，所述方法包括：（a）在衬底的第一区域中形成第一组沟槽并在衬底的第二区域中形成第二组沟槽，所述第一组沟槽沟槽具有比第二区域中的沟槽更高的纵横比; （b）将填充材料沉积在所述第一组沟槽和所述第二组沟槽中并在所述衬底的顶表面上，所述填充材料完全填充所述沟槽; （c）去除填充材料的上部; 以及（d）使用平坦化工艺从所述衬底的顶表面去除所述填充材料的所述第一和第二组沟槽中的填充材料的顶表面与所述衬底的顶表面共同平铺。

77. 发明授权

US06485355B1 Method to increase removal rate of oxide using fixed-abrasive 失效
标题翻译：使用固定研磨剂提高氧化物去除率的方法
公开(公告)号：US06485355B1
公开(公告)日：2002-11-26
申请号：US09887790
申请日：2001-06-22
申请人： Laertis Economikos , Alexander Simpson
发明人： Laertis Economikos , Alexander Simpson
IPC分类号： B24B100
CPC分类号： H01L21/31053 , B24B37/042
摘要： The invention provides fixed-abrasive chemical-mechanical polishing processes which are effective in rapidly reducing thickness of oxide layers, especially siliceous oxides. The processes of the invention are preferably characterized by at least one step involving simultaneous use of a fixed-abrasive polishing element and an aqueous liquid medium containing an abrasive. Where the original oxide layer has topographic variation, the thickness reduction technique of the invention may be preceeded by topography reduction step using a fixed-abrasive and an aqueous medium containing a polyelectrolyte for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide layer on the substrate.
摘要翻译：本发明提供固定研磨化学机械抛光方法，其有效地快速减少氧化物层的厚度，特别是二氧化硅。本发明的方法优选的特征在于包括同时使用固定研磨抛光元件和含有磨料的含水液体介质的至少一个步骤。在原始氧化物层具有地形变化的情况下，本发明的厚度减小技术可以在使用固定研磨剂和含有聚电解质的含水介质的地面还原步骤之前进行至少一部分抛光过程，所述抛光过程涉及减少跨衬底上的氧化物层的地形变化（高差）。

78. 发明授权

US06444919B1 Thin film wiring scheme utilizing inter-chip site surface wiring 失效
标题翻译：薄片布线方案采用片间现场表面布线
公开(公告)号：US06444919B1
公开(公告)日：2002-09-03
申请号：US08477054
申请日：1995-06-07
申请人： Laertis Economikos , Mukta Shaji Farooq , Michael Ford McAllister , Eric Daniel Perfecto , Chandrika Prasad , Keshav Prasad , Madhavan Swaminathan , Thomas Anthony Wassick , George White
发明人： Laertis Economikos , Mukta Shaji Farooq , Michael Ford McAllister , Eric Daniel Perfecto , Chandrika Prasad , Keshav Prasad , Madhavan Swaminathan , Thomas Anthony Wassick , George White
IPC分类号： H05K103
CPC分类号： H01L23/5382 , H01L2924/0002 , H01L2924/09701 , H05K1/0286 , H05K1/0289 , H05K3/467 , H01L2924/00
摘要： A thin film wiring scheme on a substrate. The thin film wiring scheme includes a plurality of chip connection pads at each of a first and second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines connecting directional wiring lines at the first chip site with the directional wiring lines at the second chip site.
摘要翻译：基板上的薄膜布线方案。薄膜布线方案包括在基板上的第一和第二芯片位置的每一个处的多个芯片连接焊盘，散布在第一和第二芯片位置中的每一个的芯片连接焊盘之间的多个定向布线，至少一个所述定向布线与所述第一和第二芯片位置中的每一个处的所述其它方向布线中的至少一个正交;以及多个芯片布线，其将所述第一芯片位置处的方向布线与所述定向布线连接，第二个芯片站点。

79. 发明授权

US06365328B1 Semiconductor structure and manufacturing method 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US06365328B1
公开(公告)日：2002-04-02
申请号：US09522883
申请日：2000-03-10
申请人： Hua Shen , David Kotecki , Satish Athavale , Jenny Lian , Laertis Economikos , Fen F. Jamin , Gerhard Kunkel , Nirmal Chaudhary
发明人： Hua Shen , David Kotecki , Satish Athavale , Jenny Lian , Laertis Economikos , Fen F. Jamin , Gerhard Kunkel , Nirmal Chaudhary
IPC分类号： G03F700
CPC分类号： H01L21/7687 , H01L21/76885 , H01L27/10852 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A method for forming an electrode. The method includes forming a conductive plug through a first dielectric layer. The plug extends from an upper surface of the first dielectric layer to a contact region in a semiconductor substrate. The electrode is formed photolithographically, misalignment of a mask registration in the photolithography resulting in exposing surface portions of the barrier contact. A second dielectric layer is deposited over the first dielectric layer, over side portions and top portions of the formed electrode, and over the exposed portions of barrier contact. A sacrificial material is provided on portions of the second dielectric layer disposed on lower sides of the, electrode, on portions of the second dielectric layer disposed on the first dielectric layer, and on said exposed portions of the barrier contact while exposing portions of the second dielectric layer on the top portions and upper side portions of the formed electrode. The exposed portions of the second dielectric layer are removed while leaving the portions of the second dielectric layer on the exposed portions of the barrier contact. A material is deposited over exposed portions of the first electrode and over remaining portions of the second dielectric layer in an oxidizing environment. A second electrode is formed for the storage element over the material. In forming a capacitor storage element, the portion of the second dielectric layer on the barrier contact prevents oxidation of the barrier contact during the material formation process.
摘要翻译：一种形成电极的方法。该方法包括通过第一电介质层形成导电插塞。插头从第一电介质层的上表面延伸到半导体衬底中的接触区域。光刻地形成电极，光刻中的掩模配准不对准，导致暴露屏障接触的表面部分。第二电介质层沉积在第一电介质层上，在形成的电极的侧面部分和顶部上方以及屏蔽接触的暴露部分之上。在设置在第一电介质层上的第二电介质层的部分上的第二电介质层的设置在电极的下侧的部分上以及在屏障接触的所述暴露部分上暴露第二电介质层的部分的牺牲材料在形成的电极的顶部和上侧部分上的介电层。第二介电层的暴露部分被去除，同时将第二介电层的部分留在屏障接触的暴露部分上。材料在氧化环境中沉积在第一电极的暴露部分和第二电介质层的剩余部分上。在材料上形成用于存储元件的第二电极。在形成电容器存储元件时，屏障接触部分的第二电介质层在材料形成过程中防止了屏障接触的氧化。

80. 发明授权

US06359300B1 High aspect ratio deep trench capacitor having void-free fill 有权
标题翻译：高纵横比深沟槽电容器具有无空隙填充
公开(公告)号：US06359300B1
公开(公告)日：2002-03-19
申请号：US09712708
申请日：2000-11-14
申请人： Laertis Economikos , Byeongju Park
发明人： Laertis Economikos , Byeongju Park
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/1087 , H01L29/66181
摘要： A trench capacitor comprising a substrate, a trench formed in the substrate, and conductive doped germanium or silicon-germanium alloy fill material completely filling the trench. The process for creating the capacitor comprises depositing the conductive doped germanium or silicon-germanium alloy in the trench and in a fill layer over the substrate and annealing the wafer at a temperature at which the fill layer melts and completely flows into the trench but the wafer does not melt. The process further includes depositing a silicon cap layer on top of the fill layer to prevent oxidation of the fill layer. The trench may further include one or more of a buffer layer, a metal layer, and a thermal-stress-reduction layer between the trench walls and the fill material.
摘要翻译：包括衬底，形成在衬底中的沟槽和完全填充沟槽的导电掺杂锗或硅 - 锗合金填充材料的沟槽电容器。用于制造电容器的工艺包括将导电掺杂的锗或硅 - 锗合金沉积在衬底上的沟槽和填充层中，并在填充层熔融并完全流入沟槽但晶片的温度下退火晶片不融化该方法还包括在填充层的顶部上沉积硅帽层以防止填充层氧化。沟槽还可包括缓冲层，金属层和沟槽壁与填充材料之间的热应力减小层中的一个或多个。

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