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71. 发明授权

US06778453B2 METHOD OF STORING A TEMPERATURE THRESHOLD IN AN INTEGRATED CIRCUIT, METHOD OF MODIFYING OPERATION OF DYNAMIC RANDOM ACCESS MEMORY IN RESPONSE TO TEMPERATURE, PROGRAMMABLE TEMPERATURE SENSING CIRCUIT AND MEMORY INTEGRATED CIRCUIT 失效
标题翻译：在集成电路中存储温度阈值的方法，对温度，可编程温度感测电路和存储器集成电路进行动态随机存取存储器操作的修改方法
公开(公告)号：US06778453B2
公开(公告)日：2004-08-17
申请号：US10373498
申请日：2003-02-24
申请人： Christopher B. Cooper , Ming-Bo Liu , Chris G. Martin , Troy A. Manning , Stephen L. Casper , Charles H. Dennison , Brian M. Shirley , Brian L. Brown , Shubneesh Batra
发明人： Christopher B. Cooper , Ming-Bo Liu , Chris G. Martin , Troy A. Manning , Stephen L. Casper , Charles H. Dennison , Brian M. Shirley , Brian L. Brown , Shubneesh Batra
IPC分类号： G11C704
CPC分类号： G11C7/04 , G11C7/1045 , G11C7/20 , G11C11/4072 , G11C11/4078
摘要： A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses.
摘要翻译：一种用于在集成电路中存储温度阈值的方法包括：测量集成电路的相对于温度的操作参数，计算集成电路性能超过预定规格的最大温度，并将集成电路性能中最高温度的参数存储在集成电路中的比较电路中通过在比较电路中选择性地吹入可熔设备。可熔断器件可以是反熔丝。

72. 发明授权

US06753241B2 Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry 失效
标题翻译：形成接触开口的半导体加工方法，形成电连接和互连的方法以及集成电路
公开(公告)号：US06753241B2
公开(公告)日：2004-06-22
申请号：US09956274
申请日：2001-09-18
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L213205
CPC分类号： H01L23/485 , H01L21/76802 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.
摘要翻译：描述形成接触开口，制造电互连和相关集成电路的方法。还描述了通过一个或多个本发明方法形成的集成电路。在一个实施方式中，在衬底外表面上形成具有需要电连通的接触焊盘的导电浇道或管线。导电插塞横向靠近接触垫形成，并与之一起形成有效加宽的接触垫。导电材料形成在接触开口内，接触开口被接纳在有效加宽的接触垫上的绝缘材料内。在优选的实施方式中，一对导电插塞形成在接触垫的两侧在其附近。导电插塞可以远离衬底外表面延伸一个或多或小于形成插头的导线的导线高度的距离。在前一种情况下，并且根据一个方面，这种插头可以包括与相关导电线的接触垫重叠的部分。

73. 发明授权

US06673700B2 Reduced area intersection between electrode and programming element 有权
标题翻译：电极与编程元件之间的减少交点
公开(公告)号：US06673700B2
公开(公告)日：2004-01-06
申请号：US09895020
申请日：2001-06-30
申请人： Charles H. Dennison , Guy C. Wicker , Tyler A. Lowrey , Stephen J. Hudgens , Chien Chiang , Daniel Xu
发明人： Charles H. Dennison , Guy C. Wicker , Tyler A. Lowrey , Stephen J. Hudgens , Chien Chiang , Daniel Xu
IPC分类号： H01L21326
CPC分类号： H01L27/2463 , G11C13/0004 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A method comprising forming a sacrificial layer over less than the entire portion of a contact area on a substrate, the sacrificial layer having a thickness defining an edge over the contact area, forming a spacer layer over the spacer, the spacer layer conforming to the shape of the first sacrificial layer such that the spacer layer comprises an edge portion over the contact area adjacent the first sacrificial layer edge, removing the sacrificial layer, while retaining the edge portion of the spacer layer over the contact area, forming a dielectric layer over the contact area, removing the edge portion, and forming a programmable material to the contact area formerly occupied by the edge portion. An apparatus comprising a volume of programmable material, a conductor, and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area at one end coupled to the volume of programmable material, wherein the contact area is less than the surface area at the one end.
摘要翻译：一种方法，包括在小于衬底上的接触区域的整个部分上形成牺牲层，所述牺牲层具有限定在所述接触区域上的边缘的厚度，在所述间隔物上形成间隔层，所述隔离层符合形状的第一牺牲层，使得间隔层包括邻近第一牺牲层边缘的接触区域上的边缘部分，去除牺牲层，同时将间隔物层的边缘部分保持在接触区域上方，形成介于第接触区域，去除边缘部分，并且将可编程材料形成到以前由边缘部分占据的接触区域。一种包括可编程材料体积，导体和设置在所述可编程材料体积与所述导体之间的电极的装置，所述电极在一端与所述可编程材料的体积相连接的接触区域，其中所述接触面积小于一端的表面积。

74. 发明授权

US06620672B1 SOI DRAM with buried capacitor under the digit lines utilizing a self aligning penetrating storage node contact formation 失效
标题翻译： SOI DRAM具有采用自对准穿透存储节点接触形成的数字线下的埋入式电容器
公开(公告)号：US06620672B1
公开(公告)日：2003-09-16
申请号：US10140328
申请日：2002-05-08
申请人： Charles H. Dennison , John K. Zahurak
发明人： Charles H. Dennison , John K. Zahurak
IPC分类号： H01L218242
CPC分类号： H01L27/10858 , H01L21/84 , H01L27/10888 , H01L27/10894 , H01L27/1203
摘要： A method of fabricating a memory cell is described in which an access transistor is first formed on an SOI substrate. The access transistor contains source and drain regions in a semiconductor material layer of the substrate and at least one gate stack which includes a gate region electrically connected with a word line. At least one capacitor is formed con a first side of the substrate and is electrically connected to one of the source and drain regions. At least one bit line conductor is formed on the reverse or flip side of the substrate, wherein the bit line conductor is electrically connected to the other of the source and drain regions. Self-aligned contact openings are formed through insulative material over the substrate to provide vias for the electrical connections for each of the capacitor and bit line conductor. These contact openings and the deposited contact material are substantially preserved throughout the entire fabrication process.
摘要翻译：描述了一种制造存储单元的方法，其中首先在SOI衬底上形成存取晶体管。存取晶体管包含在衬底的半导体材料层中的源极和漏极区域，以及至少一个栅极叠层，其包括与字线电连接的栅极区域。在衬底的第一侧上形成至少一个电容器，并且电连接到源区和漏区之一。至少一个位线导体形成在衬底的反面或反面上，其中位线导体电连接到源极和漏极区域中的另一个。自对准接触开口通过衬底上的绝缘材料形成，以为电容器和位线导体中的每一个提供用于电连接的通路。这些接触开口和沉积的接触材料在整个制造过程中基本保持不变。

75. 发明授权

US06605527B2 Reduced area intersection between electrode and programming element 有权
公开(公告)号：US06605527B2
公开(公告)日：2003-08-12
申请号：US09896531
申请日：2001-06-30
申请人： Charles H. Dennison , Alice T. Wang , Patel Kanaiyalal Chaturbhai , Jenn C. Chow
发明人： Charles H. Dennison , Alice T. Wang , Patel Kanaiyalal Chaturbhai , Jenn C. Chow
IPC分类号： H01L214763
CPC分类号： H01L27/1021 , H01L21/761 , H01L27/24
摘要： A method comprising forming a first dielectric layer over an electrode formed to a first contact point on a substrate, the electrode having a contact area; patterning the first dielectric layer into a body, a thickness of the first dielectric layer defining a side wall; forming at least one spacer along the side wall of the first dielectric body, the at least one spacer overlying a portion of the contact area; forming a second dielectric layer on the contact area; removing the at least one spacer; and forming a material comprising a second contact point to the contact area. An apparatus comprising a volume of programmable material; a conductor; and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area coupled to the volume of programmable material.

76. 发明授权

US06552401B1 Use of gate electrode workfunction to improve DRAM refresh 有权
公开(公告)号：US06552401B1
公开(公告)日：2003-04-22
申请号：US09721697
申请日：2000-11-27
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L2978
CPC分类号： H01L27/10873 , G11C11/406 , H01L27/10811
摘要： This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements. Current leakage is improved by this process as well.

77. 发明授权

US06440850B1 Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same 有权
标题翻译：用于与半导体结构中的薄膜的电接触的结构及其制造方法
公开(公告)号：US06440850B1
公开(公告)日：2002-08-27
申请号：US09385586
申请日：1999-08-27
申请人： Kunal R. Parekh , Mark Fischer , Charles H. Dennison
发明人： Kunal R. Parekh , Mark Fischer , Charles H. Dennison
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making the contact less prone to removal during subsequent processing steps. A top plate conformally lines a container patterned down into a subregion. A metal contact structure comprises a waist section, a contact leg, and an anchor leg. The contact leg makes contact to the top plate within the container interior. The waist section joins the top of the contact leg to the top of the anchor leg and extends over the edge of the top plate. The anchor leg extends downward through the subregion adjacent to but spaced from the container to anchor the structure in place and provide structural integrity. Accordingly, the present invention provides an improved structure for contact to a conductive thin film, having low contact resistance and an improved structural integrity.
摘要翻译：在DRAM芯片的结构内提供导电板触点的网络，以便能够在每个电荷存储区域中存储非零电压电平。改进的电池或顶板接触提供低接触电阻和改进的结构完整性，使得接触在随后的加工步骤期间更不易于去除。顶板共形地将图案化的容器图案化成一个子区域。金属接触结构包括腰部，接触腿和锚腿。接触腿与容器内部的顶板接触。腰部将接触腿的顶部连接到锚腿的顶部并且在顶板的边缘上延伸。锚腿向下延伸穿过与容器相邻但与容器间隔开的子区域，以将结构锚定在适当位置并提供结构完整性。因此，本发明提供了一种与导电薄膜接触的改进的结构，具有低的接触电阻和改进的结构完整性。

78. 发明授权

US06376358B1 Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications 有权
公开(公告)号：US06376358B1
公开(公告)日：2002-04-23
申请号：US09809666
申请日：2001-03-15
申请人： Mark Fischer , Jigish D. Trivedi , Charles H. Dennison , Todd R. Abbott , Raymond A. Turi
发明人： Mark Fischer , Jigish D. Trivedi , Charles H. Dennison , Todd R. Abbott , Raymond A. Turi
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , G11C2207/104 , H01L21/76889 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10888
摘要： A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for the operation of the DRAM and SRAM or logic. Also disclosed are systems-on-chips MIM/MIS capacitive devices produced by the inventive process.

79. 发明授权

US06331725B1 Integrated circuitry 失效
标题翻译：集成电路
公开(公告)号：US06331725B1
公开(公告)日：2001-12-18
申请号：US08951854
申请日：1997-10-16
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L2976
CPC分类号： H01L27/10852
摘要： A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conductive contact pedestal comprising the sidewall spacer, the pedestal having an outer surface which is substantially coplanar with opposing laterally adjacent electrically insulative surfaces. Also disclosed is integrated circuitry including contact pedestals. Also disclosed are methods of forming storage nodes of capacitors.
摘要翻译：形成接触基座的半导体处理方法包括：a）提供要进行电连接的节点位置; b）在节点位置上提供绝缘电介质材料; c）在所述节点位置上将接触开口蚀刻到所述绝缘介电材料中至不足以向外暴露所述节点位置的程度，所述接触开口具有基部; d）在绝缘电介质材料之上提供间隔层至接触开口内至少小于完全填充接触开口的厚度; e）各向异性地蚀刻间隔层以在接触开口内形成侧壁间隔物; f）在形成侧壁间隔物之后，通过接触开口基底蚀刻以向外暴露节点位置; g）用导电材料将接触开口填充到节点位置; h）使侧壁间隔物导电; 以及i）蚀刻所述导电材料以形成包括所述侧壁间隔物的导电接触基座，所述基座具有与相对的横向相邻的电绝缘表面基本上共面的外表面。还公开了包括接触基座的集成电路。还公开了形成电容器的存储节点的方法。

80. 发明授权

US06323087B1 Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry 失效
公开(公告)号：US06323087B1
公开(公告)日：2001-11-27
申请号：US09565196
申请日：2000-05-04
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L218247
CPC分类号： H01L23/485 , H01L21/76802 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.

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