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1. 发明授权

US06440850B1 Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same 有权
标题翻译：用于与半导体结构中的薄膜的电接触的结构及其制造方法
公开(公告)号：US06440850B1
公开(公告)日：2002-08-27
申请号：US09385586
申请日：1999-08-27
申请人： Kunal R. Parekh , Mark Fischer , Charles H. Dennison
发明人： Kunal R. Parekh , Mark Fischer , Charles H. Dennison
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making the contact less prone to removal during subsequent processing steps. A top plate conformally lines a container patterned down into a subregion. A metal contact structure comprises a waist section, a contact leg, and an anchor leg. The contact leg makes contact to the top plate within the container interior. The waist section joins the top of the contact leg to the top of the anchor leg and extends over the edge of the top plate. The anchor leg extends downward through the subregion adjacent to but spaced from the container to anchor the structure in place and provide structural integrity. Accordingly, the present invention provides an improved structure for contact to a conductive thin film, having low contact resistance and an improved structural integrity.
摘要翻译：在DRAM芯片的结构内提供导电板触点的网络，以便能够在每个电荷存储区域中存储非零电压电平。改进的电池或顶板接触提供低接触电阻和改进的结构完整性，使得接触在随后的加工步骤期间更不易于去除。顶板共形地将图案化的容器图案化成一个子区域。金属接触结构包括腰部，接触腿和锚腿。接触腿与容器内部的顶板接触。腰部将接触腿的顶部连接到锚腿的顶部并且在顶板的边缘上延伸。锚腿向下延伸穿过与容器相邻但与容器间隔开的子区域，以将结构锚定在适当位置并提供结构完整性。因此，本发明提供了一种与导电薄膜接触的改进的结构，具有低的接触电阻和改进的结构完整性。

2. 发明授权

US06710420B2 Semiconductor construction of a trench 有权
标题翻译：半导体构造的沟槽
公开(公告)号：US06710420B2
公开(公告)日：2004-03-23
申请号：US10241923
申请日：2002-09-11
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
摘要翻译：一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

3. 发明授权

US06482707B1 Method of improving static refresh 有权
标题翻译：改善静态刷新的方法
公开(公告)号：US06482707B1
公开(公告)日：2002-11-19
申请号：US09532094
申请日：2000-03-21
申请人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
发明人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28247 , H01L29/6656
摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.
摘要翻译：公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成扩散区的双层覆盖离子注入方法。该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对扩散区。第一次毯式离子注入工艺具有第一能级和剂量。该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。第二次毯子离子注入过程具有第二能量水平和剂量。所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

4. 发明授权

US06410951B1 Structure for improving static refresh 有权
公开(公告)号：US06410951B1
公开(公告)日：2002-06-25
申请号：US09822249
申请日：2001-04-02
申请人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
发明人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
IPC分类号： H01L21336
摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.

5. 发明授权

US06406977B2 Isolation region forming methods 失效
标题翻译：隔离区形成方法
公开(公告)号：US06406977B2
公开(公告)日：2002-06-18
申请号：US09521095
申请日：2000-03-07
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
摘要翻译：一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

6. 发明授权

US07119397B2 Double blanket ion implant method and structure 有权
标题翻译：双层离子注入法和结构
公开(公告)号：US07119397B2
公开(公告)日：2006-10-10
申请号：US10768081
申请日：2004-02-02
申请人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
发明人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
IPC分类号： H01L29/06
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28247 , H01L29/6656
摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.
摘要翻译：公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成扩散区的双层覆盖离子注入方法。该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对扩散区。第一次毯式离子注入工艺具有第一能级和剂量。该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。第二次毯子离子注入过程具有第二能量水平和剂量。所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

7. 发明授权

US06605532B1 Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same 有权
公开(公告)号：US06605532B1
公开(公告)日：2003-08-12
申请号：US09858121
申请日：2001-05-15
申请人： Kunal R. Parekh , Mark Fischer , Charles H. Dennison
发明人： Kunal R. Parekh , Mark Fischer , Charles H. Dennison
IPC分类号： H01L214763
CPC分类号： H01L23/485 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making the contact less prone to removal during subsequent processing steps. A top plate conformally lines a container patterned down into a subregion. A metal contact structure comprises a waist section, a contact leg, and an anchor leg. The contact leg makes contact to the top plate within the container interior. The waist section joins the top of the contact leg to the top of the anchor leg and extends over the edge of the top plate. The anchor leg extends downward through the subregion adjacent to but spaced from the container to anchor the structure in place and provide structural integrity. Accordingly, the present invention provides an improved structure for contact to a conductive thin film, having low contact resistance and an improved structural integrity.

8. 发明授权

US06372601B1 Isolation region forming methods 失效
公开(公告)号：US06372601B1
公开(公告)日：2002-04-16
申请号：US09146838
申请日：1998-09-03
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L21762
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

9. 发明授权

US06693014B2 Method of improving static refresh 有权
标题翻译：改善静态刷新的方法
公开(公告)号：US06693014B2
公开(公告)日：2004-02-17
申请号：US10285488
申请日：2002-11-01
申请人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
发明人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28247 , H01L29/6656
摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.
摘要翻译：公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成扩散区的双层覆盖离子注入方法。该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一毯式离子注入工艺在与沟道区相邻的区域中形成第一对扩散区。第一次毯式离子注入工艺具有第一能级和剂量。该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。第二次毯子离子注入过程具有第二能量水平和剂量。所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

10. 发明授权

US06329267B1 Isolation region forming methods 失效
公开(公告)号：US06329267B1
公开(公告)日：2001-12-11
申请号：US09520739
申请日：2000-03-07
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L21762
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

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