专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US06774432B1 UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL 有权
标题翻译：紫外线阻挡层，用于降低BEOL中SONOS双位闪存器件的UV感应充电
公开(公告)号：US06774432B1
公开(公告)日：2004-08-10
申请号：US10358589
申请日：2003-02-05
申请人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
发明人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
IPC分类号： H01L29792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L23/552 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device, including a SONOS flash memory cell; and at least one UV-protective layer, in which the UV-protective layer comprises a substantially UV-opaque material, is provided. In one embodiment, the device includes a substantially UV-opaque contact cap layer.
摘要翻译：一种保护SONOS闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造SONOS闪存单元; 并且在所述SONOS闪存单元上沉积至少一个UV保护层，所述UV保护层包括基本上不透紫外线的材料。 SONOS闪存设备，包括SONOS闪存单元; 以及至少一个UV保护层，其中UV保护层包括基本上不透紫外线的材料。在一个实施例中，该装置包括基本上不透紫外线的接触盖层。

72. 发明授权

US06617215B1 Memory wordline hard mask 有权
标题翻译：内存字线硬掩模
公开(公告)号：US06617215B1
公开(公告)日：2003-09-09
申请号：US10109235
申请日：2002-03-27
申请人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
发明人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/0332 , H01L21/32139 , H01L27/115
摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.
摘要翻译：用于MirrorBit（R）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质材料。植入第一和第二位线，并存放字线材料。硬掩模材料沉积在字线材料上。硬掩模材料是具有沉积而不是生长的特征的材料。光致抗蚀剂材料沉积在字线材料上并被图案化以形成图案化的硬掩模。去除图案化的光致抗蚀剂材料。使用图案化的硬掩模处理字线材料以形成字线。去除图案化的硬掩模材料。

73. 发明授权

US06514874B1 Method of using controlled resist footing on silicon nitride substrate for smaller spacing of integrated circuit device features 失效
标题翻译：在氮化硅衬底上使用受控抗蚀剂基底的方法，用于较小间距的集成电路器件特征
公开(公告)号：US06514874B1
公开(公告)日：2003-02-04
申请号：US09875635
申请日：2001-06-06
申请人： James Jiahua Yu , Bhanwar Singh , Angela T. Hui
发明人： James Jiahua Yu , Bhanwar Singh , Angela T. Hui
IPC分类号： H01L21461
CPC分类号： H01L21/31144
摘要： A method of fabricating an integrated circuit can include providing a layer of silicon nitride over a semiconductor substrate where the layer of silicon nitride has a first thickness selected based on a desired size of extensions; providing a layer of photoresist material over the layer of silicon nitride; patterning the layer of photoresist to form photoresist features being separated at the top of the photoresist features by one minimum lithographic feature and etching a portion of the layer of silicon nitride to form a hole for an integrated circuit device feature. The photoresist features include extensions at the bottom of the photoresist features. The extensions define footings. These footings reduce the separation at the bottom of the photoresist features. As such, exposed portions of the layer of silicon nitride are less than one minimum lithographic feature in width.
摘要翻译：制造集成电路的方法可以包括在半导体衬底上提供氮化硅层，其中氮化硅层具有基于期望的扩展尺寸选择的第一厚度; 在氮化硅层上提供一层光致抗蚀剂材料; 图案化光致抗蚀剂层以形成光致抗蚀剂特征，其通过一个最小光刻特征在光致抗蚀剂特征的顶部分离，并蚀刻氮化硅层的一部分以形成用于集成电路器件特征的孔。光致抗蚀剂特征包括在光刻胶特征底部的延伸部分。扩展名定义了基础。这些底脚减少了光刻胶特征底部的分离。因此，氮化硅层的暴露部分的宽度小于一个最小光刻特征。

74. 发明授权

US06475867B1 Method of forming integrated circuit features by oxidation of titanium hard mask 失效
标题翻译：通过钛硬掩模氧化形成集成电路特征的方法
公开(公告)号：US06475867B1
公开(公告)日：2002-11-05
申请号：US09824416
申请日：2001-04-02
申请人： Angela T. Hui , Kouros Ghandehari , Bhanwar Singh
发明人： Angela T. Hui , Kouros Ghandehari , Bhanwar Singh
IPC分类号： H07L21336
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338
摘要： An exemplary method of forming integrated circuit device features by oxidization of titanium hard mask is described. This method can include providing a photoresist pattern of photoresist features over a first layer of material deposited over a second layer of material; etching the first layer of material according to the photoresist pattern to form material features; oxidizing exposed portions of the material features where the material features are made of a material which expands during oxidation; and etching the second layer of material according to the material features which have expanded as a result of oxidation. Advantageously, the expansion of the material features results in a smaller distance between material features than the distance between photoresist features.
摘要翻译：描述了通过钛硬掩模的氧化形成集成电路器件特征的示例性方法。该方法可以包括在沉积在第二材料层上的第一材料层上提供光致抗蚀剂特征的光致抗蚀剂图案; 根据光致抗蚀剂图案蚀刻第一层材料以形成材料特征; 氧化材料特征的暴露部分，其中材料特征由在氧化期间膨胀的材料制成; 并根据由于氧化而膨胀的材料特征蚀刻第二层材料。有利地，材料特征的扩展导致材料特征之间的距离比光致抗蚀剂特征之间的距离更小。

75. 发明授权

US06465835B1 Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate 有权
标题翻译：通过在轻掺杂漏极和栅极之间使用双重隔离/覆盖层，对闪存技术进行充电增益/电荷损耗结漏电防护
公开(公告)号：US06465835B1
公开(公告)日：2002-10-15
申请号：US09487964
申请日：2000-01-18
申请人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
发明人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： An improved flash memory device having core stacks and periphery stacks which are protected by first and second thin side walls, side spacers over the side walls, and an HTO layer over the stacks, and side spacer. The flash memory device has an intermetallic dielectric layer placed over the HTO layer. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The additional first and second side walls reduce current leakage between core stacks and the tungsten plug and help to protect the stacks during fabrication.
摘要翻译：具有由第一和第二薄侧壁，侧壁上的侧隔离物以及叠层上的HTO层和侧隔板保护的芯堆叠和外围堆叠的改进的闪存器件。闪存器件具有置于HTO层上的金属间介电层。将钨塞放置在金属间介电层中以提供与闪存器件的漏极的电连接。附加的第一和第二侧壁减小了芯堆叠和钨插头之间的电流泄漏，并有助于在制造期间保护堆叠。

76. 发明授权

US06431182B1 Plasma treatment for polymer removal after via etch 有权
标题翻译：通过蚀刻后的聚合物去除的等离子体处理
公开(公告)号：US06431182B1
公开(公告)日：2002-08-13
申请号：US09427861
申请日：1999-10-27
申请人： Mohammad R. Rakhshandehroo , Mark S. Chang , Angela T. Hui
发明人： Mohammad R. Rakhshandehroo , Mark S. Chang , Angela T. Hui
IPC分类号： B08B600
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/76814
摘要： A method and article of manufacture of a via in a semiconductor layered device. The method can include applying an OH/H containing plasma, such as H2O or O2 or a forming gas, to a via which has been etched in a layer of the device. A mixture of oxygen and fluorine-based plasma is applied to complete cleaning of the via to provide a clean via with very little loss of dimensional and surface quality. In another aspect the OH/H containing plasma and the oxygen and fluorine-based plasma are applied together to clean the via.
摘要翻译：半导体分层器件中的通孔的制造方法和制造方法。该方法可以包括将OH / H等离子体（例如H 2 O或O 2或形成气体）施加到在器件的层中被蚀刻的通孔。施加氧和氟基等离子体的混合物以完成通孔的清洁以提供清洁的通孔，其尺寸和表面质量几乎没有损失。另一方面，将包含OH / H的等离子体和基于氧和氟的等离子体一起施加以清洁通孔。

77. 发明授权

US06420752B1 Semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：具有使用衬垫氧化物层的自对准触点的半导体器件
公开(公告)号：US06420752B1
公开(公告)日：2002-07-16
申请号：US09502163
申请日：2000-02-11
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种用于最小化自动掺杂问题的半导体器件。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并且与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触并且用作介电层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

78. 发明授权

US08652907B2 Integrating transistors with different poly-silicon heights on the same die 有权
标题翻译：将晶体管与不同的多晶硅高度集成在同一芯片上
公开(公告)号：US08652907B2
公开(公告)日：2014-02-18
申请号：US13071385
申请日：2011-03-24
申请人： Chuan Lin , Hidehiko Shiraiwa , Bradley Marc Davis , Lei Xue , Simon S. Chan , Kenichi Ohtsuka , Angela T. Hui , Scott Allan Bell
发明人： Chuan Lin , Hidehiko Shiraiwa , Bradley Marc Davis , Lei Xue , Simon S. Chan , Kenichi Ohtsuka , Angela T. Hui , Scott Allan Bell
IPC分类号： H01L21/28 , H01L21/8234
CPC分类号： H01L29/4916 , H01L21/28044 , H01L21/823456 , H01L27/11543 , H01L27/11546 , H01L29/78
摘要： A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.
摘要翻译：提供一种制造集成电路的方法，该集成电路包括具有不同多晶硅栅极结构的第一区域和第二区域。该方法包括在第一和第二区域上沉积第一多晶硅层，并在第二区域内在第一多晶硅层上沉积氧化物层。在第一多晶硅层和氧化物区域上沉积第二多晶硅层。然后剥离位于氧化物区域上方的第二多晶硅层的一部分。

79. 发明申请

US20120241871A1 INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE 有权
标题翻译：在相同的模具上集成不同多晶硅高精度晶体管
公开(公告)号：US20120241871A1
公开(公告)日：2012-09-27
申请号：US13071385
申请日：2011-03-24
申请人： Chuan Lin , Hidehiko Shiraiwa , Bradley Marc Davis , Lei Xue , Simon S. Chan , Kenichi Ohtsuka , Angela T. Hui , Scott Allan Bell
发明人： Chuan Lin , Hidehiko Shiraiwa , Bradley Marc Davis , Lei Xue , Simon S. Chan , Kenichi Ohtsuka , Angela T. Hui , Scott Allan Bell
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L29/4916 , H01L21/28044 , H01L21/823456 , H01L27/11543 , H01L27/11546 , H01L29/78
摘要： A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.
摘要翻译：提供一种制造集成电路的方法，该集成电路包括具有不同多晶硅栅极结构的第一区域和第二区域。该方法包括在第一和第二区域上沉积第一多晶硅层，并在第二区域内在第一多晶硅层上沉积氧化物层。在第一多晶硅层和氧化物区域上沉积第二多晶硅层。然后剥离位于氧化物区域上方的第二多晶硅层的一部分。

80. 发明授权

US08067314B2 Gate trim process using either wet etch or dry etch approach to target CD for selected transistors 有权
标题翻译：使用湿蚀刻或干法蚀刻方法对所选晶体管靶CD进行栅极修整处理
公开(公告)号：US08067314B2
公开(公告)日：2011-11-29
申请号：US12424023
申请日：2009-04-15
申请人： Bradley M. Davis , Jihwan Choi , Angela T. Hui
发明人： Bradley M. Davis , Jihwan Choi , Angela T. Hui
IPC分类号： H01L21/76
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/28132 , H01L21/823456
摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.
摘要翻译：公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式