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71. 发明授权

US07136955B2 Expansion adapter supporting both PCI and AGP device functions 有权
标题翻译：扩展适配器支持PCI和AGP设备功能
公开(公告)号：US07136955B2
公开(公告)日：2006-11-14
申请号：US10980624
申请日：2004-11-03
申请人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
发明人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
IPC分类号： G06F13/00 , G06F13/20 , G06F13/36
CPC分类号： G06F13/385 , G06F2213/0024
摘要： An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.
摘要翻译：扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块。

72. 发明申请

US20060184757A1 Data memory controller that supports data bus invert 有权
公开(公告)号：US20060184757A1
公开(公告)日：2006-08-17
申请号：US11402700
申请日：2006-04-11
申请人： Bi-Yun Yeh , Jiin Lai , Sheng-Chung Wu
发明人： Bi-Yun Yeh , Jiin Lai , Sheng-Chung Wu
IPC分类号： G06F13/00
CPC分类号： G06F13/1668 , G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.

73. 发明申请

US20050097254A1 Expansion adapter supporting both PCI and AGP device functions 有权
标题翻译：扩展适配器支持PCI和AGP设备功能
公开(公告)号：US20050097254A1
公开(公告)日：2005-05-05
申请号：US10980624
申请日：2004-11-03
申请人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
发明人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
IPC分类号： G06F13/36 , G06F13/38
CPC分类号： G06F13/385 , G06F2213/0024
摘要： An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device
摘要翻译：扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块

74. 发明申请

US20050086019A1 METHOD AND APPARATUS FOR TESTING A BRIDGE CIRCUIT 有权
标题翻译：测试电路的方法和装置
公开(公告)号：US20050086019A1
公开(公告)日：2005-04-21
申请号：US10904047
申请日：2004-10-21
申请人： Biyun Yeh , Victor Wu , Jiin Lai
发明人： Biyun Yeh , Victor Wu , Jiin Lai
IPC分类号： G01R31/28 , G01R31/317 , G06F19/00 , G01R31/00
CPC分类号： G01R31/31725 , G01R31/31727
摘要： A method and an apparatus for testing a bridge circuit. The method includes inputting a first test clock to a first conversion unit for triggering the first conversion unit to transfer a test data to a second conversion unit according to rising edges of the first test clock, inputting a second test clock to the second conversion unit for triggering the second conversion unit to output an output data according to falling edges of the second test clock, and controlling the first test clock and the second test clock so that the rising edges of the second test clock are not synchronized to the rising edges of the first test clock. A frequency of the first test clock is an even multiple of a frequency of the second test clock.
摘要翻译：一种测试桥接电路的方法和装置。该方法包括将第一测试时钟输入到第一转换单元，用于触发第一转换单元根据第一测试时钟的上升沿将测试数据传送到第二转换单元，向第二转换单元输入第二测试时钟触发所述第二转换单元根据所述第二测试时钟的下降沿输出输出数据，并且控制所述第一测试时钟和所述第二测试时钟，使得所述第二测试时钟的上升沿不与所述第二测试时钟的上升沿同步第一个测试时钟。第一测试时钟的频率是第二测试时钟的频率的偶数倍。

75. 发明授权

US06546448B1 Method and apparatus for arbitrating access to a PCI bus by a plurality of functions in a multi-function master 有权
标题翻译：用于通过多功能主机中的多个功能来仲裁对PCI总线的访问的方法和装置
公开(公告)号：US06546448B1
公开(公告)日：2003-04-08
申请号：US09440764
申请日：1999-11-16
申请人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Chi-Che Tsai
发明人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Chi-Che Tsai
IPC分类号： G06F1314
CPC分类号： G06F13/362
摘要： Method and apparatus for arbitrating access to a pci bus by a plurality of functions in a multi-function master. The arbitrating method is performed among the multiple functions of a multi-function master. The arbiter includes a rotating inquiry scheduler (RIS) and a heuristic inquiry initiator (HII). The RIS receives the local inquiry signal from the functional circuit and stores it. According to the local inquiry signal, a bus inquiry signal is generated and sent to the HII, and is sent to the PCI bus to request a use of the PCI bus. If the PCI bus responds a delay transaction termination, the HII can repeatedly send the bus inquiry signal to the PCI bus until the PCI bus grants the privilege to use the PCI bus. The HII then informs the RIS, which arranges the functional circuit to transmit data through the PCI bus.
摘要翻译：用于通过多功能主机中的多个功能来仲裁对pci总线的访问的方法和装置。在多功能主机的多个功能之间执行仲裁方法。仲裁器包括旋转查询调度程序（RIS）和启发式查询启动器（HII）。 RIS从功能电路接收本地查询信号并存储。根据本地查询信号，生成总线查询信号并将其发送到HII，并发送到PCI总线以请求使用PCI总线。如果PCI总线响应延迟事务终止，则HII可以将总线查询信号重复发送到PCI总线，直到PCI总线授予使用PCI总线的权限。然后，HII通知RIS，该RIS将功能电路通过PCI总线传输数据。

76. 发明授权

US06484281B1 Software-based simulation system capable of simulating the combined functionality of a north bridge test module and a south bridge test module 有权
标题翻译：基于软件的仿真系统，能够模拟北桥测试模块和南桥测试模块的组合功能
公开(公告)号：US06484281B1
公开(公告)日：2002-11-19
申请号：US09459763
申请日：1999-12-13
申请人： Hsuan-Yi Wang , Jiin Lai , Nai-Shung Chang
发明人： Hsuan-Yi Wang , Jiin Lai , Nai-Shung Chang
IPC分类号： G01R3128
CPC分类号： G01R31/318342
摘要： A software-based simulation system is provided, which can provide the combined functionality of a South Bridge test module and a North Bridge test module based solely on either one of the two modules, i.e., either the South Bridge test module or the North Bridge test module without having to use both. This software-based simulation system is characterized in the use of a PCI master modeling circuit and a PCI slave modeling circuit which are capable of simulating the functionality of the North Bridge chipset in the case that only the South Bridge chipset and no North Bridge chipset is included in the simulation system, and are further capable of simulating the functionality of the South Bridge chipset in the case that only the North Bridge chipset and no South Bridge chipset is included in the simulation system.
摘要翻译：提供了一个基于软件的仿真系统，可以提供南桥测试模块和北桥测试模块的组合功能，该模块仅基于两个模块之一，即南桥测试模块或北桥测试模块，而不必使用两者。该基于软件的仿真系统的特征在于使用PCI主建模电路和PCI从属建模电路，其能够模拟北桥芯片组的功能，仅在南桥芯片组和北桥芯片组为包括在仿真系统中，并且在模拟系统中仅包括北桥芯片组且没有南桥芯片组的情况下，还能够模拟南桥芯片组的功能。

77. 发明授权

US6020774A Gated clock tree synthesis method for the logic design 失效
标题翻译：门控时钟树的逻辑设计合成方法
公开(公告)号：US6020774A
公开(公告)日：2000-02-01
申请号：US121296
申请日：1998-07-23
申请人： You-Ming Chiu , Jiin Lai
发明人： You-Ming Chiu , Jiin Lai
IPC分类号： G06F1/10 , G06F17/50 , H03K1/04
CPC分类号： G06F17/505 , G06F1/10 , G06F2217/62
摘要： A gated clock tree synthesis (CTS) method is provided for the purpose of synthesizing a gate array logic circuit to allow optimal topological arrangement of the gate array on the logic circuit. This in turn allows the logic circuit to operate more efficiently. The logic circuit includes at least one clock generator, a plurality of control gates each having one input end connected to a control signal and the other input end connected to receive the output clock signal from the clock generator, a plurality of first logic elements that are directly driven by the output clock signal from the clock generator, and a plurality of second logic elements that are driven by the gated clock signal outputted from each of the control gates under control by the control signal. The gated CTS method comprises the steps of grouping the first logic elements into a plurality of groups, connecting each group of the first logic elements via a first buffer to one of the control gates, connecting each of the second logic elements via a second buffer to the clock generator, and connecting one input end of each of the control gates to the clock generator.
摘要翻译：提供门控时钟树合成（CTS）方法用于合成门阵列逻辑电路以允许逻辑电路上的门阵列的最佳拓扑排列。这又允许逻辑电路更有效地操作。逻辑电路包括至少一个时钟发生器，多个控制栅极，每个控制栅极具有一个连接到控制信号的输入端，另一个输入端连接以从时钟发生器接收输出时钟信号;多个第一逻辑元件，由来自时钟发生器的输出时钟信号直接驱动，以及多个第二逻辑元件，其由控制信号控制的每个控制门输出的门控时钟信号驱动。门控CTS方法包括以下步骤：将第一逻辑元件分组成多个组，将每组第一逻辑元件经由第一缓冲器连接到控制门之一，将第二逻辑元件经由第二缓冲器连接到时钟发生器，并且将每个控制门的一个输入端连接到时钟发生器。

78. 发明授权

US08812782B2 Memory management system and memory management method 有权
标题翻译：内存管理系统和内存管理方法
公开(公告)号：US08812782B2
公开(公告)日：2014-08-19
申请号：US12694470
申请日：2010-01-27
申请人： Jian Li , Jiin Lai , Shan-Na Pang , Zhi-Qiang Hui , Di Dai
发明人： Jian Li , Jiin Lai , Shan-Na Pang , Zhi-Qiang Hui , Di Dai
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/1036
摘要： A memory management system and method include and use a cache buffer (such as a table look-aside buffer, TLB), a memory mapping table, a scratchpad cache, and a memory controller. The cache buffer is configured to store a plurality of data structures. The memory mapping table is configured to store a plurality of addresses of the data structures. The scratchpad cache is configured to store the base address of the data structures. The memory controller is configured to control reading and writing in the cache buffer and the scratchpad cache. The components are operable together under control of the memory controller to facilitate effective searching of the data structures in the memory management system.
摘要翻译：存储器管理系统和方法包括并使用高速缓冲存储器（例如，表查看缓冲器，TLB），存储器映射表，暂存器缓存和存储器控制器。高速缓存缓冲器被配置为存储多个数据结构。存储器映射表被配置为存储数据结构的多个地址。暂存器缓存被配置为存储数据结构的基址。存储器控制器被配置为控制高速缓冲存储器和暂存器缓存中的读写。这些组件在存储器控制器的控制下一起可操作，以便有效地搜索存储器管理系统中的数据结构。

79. 发明授权

US08656074B2 Data transmission system and method thereof 有权
标题翻译：数据传输系统及其方法
公开(公告)号：US08656074B2
公开(公告)日：2014-02-18
申请号：US12862134
申请日：2010-08-24
申请人： Jiin Lai , Buheng Xu , Jinkuan Tang
发明人： Jiin Lai , Buheng Xu , Jinkuan Tang
IPC分类号： G06F13/12 , G06F13/38
CPC分类号： G06F13/385 , G06F11/08 , G06F13/00 , G06F13/12
摘要： A data transmission system is provided. The data transmission system includes a first control circuit coupled to a first device, a translation circuit coupled to the first control circuit and a second control circuit coupled to the translation circuit. The first control circuit decodes a first format data packet sent by the first device. The translation circuit receives the decoded first format data packet and translates the decoded first format data packet into a second format data packet. The second control circuit transmits the second format data packet to a host. A data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device.
摘要翻译：提供数据传输系统。数据传输系统包括耦合到第一设备的第一控制电路，耦合到第一控制电路的平移电路和耦合到转换电路的第二控制电路。第一控制电路解码由第一设备发送的第一格式数据分组。翻译电路接收解码的第一格式数据分组，并将解码的第一格式数据分组转换为第二格式数据分组。第二控制电路将第二格式数据包发送到主机。第一设备的数据传输速率比第二设备的数据传输速率慢，并且数据传输系统向后兼容于第一设备。

80. 发明授权

US08452909B2 USB transaction translator and a micro-frame synchronization method adaptable to an USB in isochronous transaction 有权
标题翻译： USB事务转换器和适用于同步事务中的USB的微帧同步方法
公开(公告)号：US08452909B2
公开(公告)日：2013-05-28
申请号：US12959277
申请日：2010-12-02
申请人： Jinkuan Tang , Jiin Lai , Buheng Xu , Hui Jiang
发明人： Jinkuan Tang , Jiin Lai , Buheng Xu , Hui Jiang
IPC分类号： G06F13/20 , G06F13/38
CPC分类号： G06F13/385 , G06F13/4059
摘要： The present invention is directed to a universal serial bus (USB) transaction translator and a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, wherein the counting value of the SOF counter is compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves the predefined value or is greater than the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host.
摘要翻译：本发明涉及通用串行总线（USB）事务转换器和微帧同步方法。设备接口经由设备总线耦合到设备，并且主机接口通过主机总线耦合到主机，其中主机USB版本高于设备USB版本。配置为存储数据的至少两个缓冲器被布置在设备接口和主机接口之间。控制器交替地将数据存储在缓冲器中。使用起始帧（SOF）计数器对SOF分组进行计数，其中将SOF计数器的计数值与预定义的值进行比较。具体地，当计数值达到预定义值或大于预定值时，控制器复位用于发送SOF分组的SOF定时器，使得来自主机的SOF分组和等时时间戳分组（ITP）以相同的方式发送时间。此外，控制器根据来自主机的ITP延迟SOF分组的发送一段时间。

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