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71. 发明申请

US20070122988A1 METHODS OF FORMING SEMICONDUCTOR DEVICES USING EMBEDDED L-SHAPE SPACERS 失效
标题翻译：使用嵌入式L形形状间隔件形成半导体器件的方法
公开(公告)号：US20070122988A1
公开(公告)日：2007-05-31
申请号：US11164567
申请日：2005-11-29
申请人： Zhijiong Luo , Young Teh , Atul Ajmera
发明人： Zhijiong Luo , Young Teh , Atul Ajmera
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/6656 , H01L29/6653
摘要： A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends over a portion of the substrate a predetermined distance from a lateral edge of the L-shaped spacer. And removing oxide layers to expose the L-shape spacers.
摘要翻译：提供一种形成嵌入L形间隔件的半导体器件的方法。该方法包括在衬底的栅极区域的每一侧上限定L形间隔物并将L形间隔物嵌入氧化物层中，使得氧化物层在衬底的一部分上延伸超过 L形间隔物。并且除去氧化物层以露出L形间隔物。

72. 发明授权

US07202164B2 Method of forming ultra thin silicon oxynitride for gate dielectric applications 有权
标题翻译：形成用于栅极电介质应用的超薄氮氧化硅的方法
公开(公告)号：US07202164B2
公开(公告)日：2007-04-10
申请号：US10992894
申请日：2004-11-19
申请人： Jinping Liu , Hwa Weng Koh , Dong Kyun Sohn , Liang Choo Hsia
发明人： Jinping Liu , Hwa Weng Koh , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/8238
CPC分类号： H01L21/0214 , H01L21/02238 , H01L21/02332 , H01L21/265 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/518
摘要： A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A nitridation process is performed. An optional high temperature annealing step may be performed.
摘要翻译：公开了一种形成栅介质层的方法。该方法包括以下步骤。提供了具有硅区域的衬底，所述硅区域包含要在其上设置栅极电介质的表面。在表面上形成氧化物。在氧化物层上形成硅层。进行氮化处理。可以进行可选的高温退火步骤。

73. 发明申请

US20070032026A1 Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing 有权
标题翻译：使用激光退火形成应变Si沟道和Si1-xGex源极/漏极结构
公开(公告)号：US20070032026A1
公开(公告)日：2007-02-08
申请号：US11195196
申请日：2005-08-02
申请人： Kuang Ong , Kin Pey , King Chui , Ganesh Samudra , Yee Yeo , Yung Chong
发明人： Kuang Ong , Kin Pey , King Chui , Ganesh Samudra , Yee Yeo , Yung Chong
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02675 , H01L21/268 , H01L21/7624 , H01L29/165 , H01L29/665 , H01L29/66628 , Y10S438/938
摘要： A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.
摘要翻译：已经开发了通过形成相邻的硅 - 锗源/漏区来形成用于MOSFET器件的应变沟道区的工艺。该方法的特征在于硅 - 锗层的覆盖沉积，或硅 - 锗层在源极/漏极延伸区域的暴露部分上的选择性生长。激光退火程序通过消耗硅 - 锗层的底部部分和下面的源极/漏极区域的顶部部分而导致硅 - 锗源极/漏极区域的形成。通过经由激光退火形成硅 - 锗源/漏区的优化可以通过在沉积硅 - 锗层之前施加到源/漏区的暴露部分的前非晶化注入（PAI）程序来实现。在激光退火过程之后，硅 - 锗层的未反应顶部被选择性地去除。

74. 发明申请

US20060286797A1 Grain boundary blocking for stress migration and electromigration improvement in CU interconnects 有权
标题翻译：用于CU互连中的应力迁移和电迁移改进的谷物边界阻塞
公开(公告)号：US20060286797A1
公开(公告)日：2006-12-21
申请号：US11153747
申请日：2005-06-15
申请人： Fan Zhang , Kho Liep , Alex See , Cheng-Cheh Tou , Xiaomei Bu , Tae Lee , Liang Hsia
发明人： Fan Zhang , Kho Liep , Alex See , Cheng-Cheh Tou , Xiaomei Bu , Tae Lee , Liang Hsia
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76859 , H01L21/76856 , H01L21/76864
摘要： Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.
摘要翻译：用于形成具有在顶表面附近的掺杂区域的铜互连的结构和方法的示例实施例。掺杂区域已经植入了阻挡晶界并减少应力和电迁移的合金元素。在第一示例性实施例中，在合金元素植入期间，阻挡层留在金属间介电层上。稍后通过平坦化处理去除阻挡层。在第二示例性实施例中，在合金元素注入之前去除阻挡层，并且硬掩模阻止合金元素被注入在金属间介电层中。

75. 发明授权

US07141854B2 Double-gated silicon-on-insulator (SOI) transistors with corner rounding 有权
标题翻译：双栅绝缘体（SOI）晶体管，带圆角
公开(公告)号：US07141854B2
公开(公告)日：2006-11-28
申请号：US11174857
申请日：2005-07-05
申请人： Yong Meng Lee , Da Jin , David Vigar
发明人： Yong Meng Lee , Da Jin , David Vigar
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L23/62
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/7854 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double gated transistor.
摘要翻译：形成具有圆形有源区域以提高GOI和漏电流控制的双门控晶体管的方法尤其包括以下步骤。图案化SOI衬底，并且在图案化的上SOI硅层的暴露侧壁上形成圆形氧化物层。在暴露的图案化的顶部氧化物层和上部SOI硅层的暴露部分之上形成具有限定栅极的开口的虚设层。在底切下面的SOI氧化物层中形成底切，去除氧化物层的暴露的栅极区域部分。去除栅极区域内的圆形氧化物层的部分，并且在该结构的一部分上形成共形氧化物层。在第二图案化虚拟层开口内形成栅极，去除图案化虚拟层以形成双门控晶体管。

76. 发明授权

US07135743B2 Electrostatic discharge protection device with complementary dual drain implant 有权
公开(公告)号：US07135743B2
公开(公告)日：2006-11-14
申请号：US11291757
申请日：2005-12-01
申请人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Michael Cheng
发明人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Michael Cheng
IPC分类号： H01L23/62
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1083 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

77. 发明申请

US20060249794A1 Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS 有权
标题翻译：腐蚀后去除间隔物的方法，以增强接触蚀刻停止衬垫在MOS上的应力
公开(公告)号：US20060249794A1
公开(公告)日：2006-11-09
申请号：US11122666
申请日：2005-05-04
申请人： Young Teh , Yong Lee , Chung Lai , Wenhe Lin , Khee Lim , Wee Tan , John Sudijono , Hui Koh , Liang Hsia
发明人： Young Teh , Yong Lee , Chung Lai , Wenhe Lin , Khee Lim , Wee Tan , John Sudijono , Hui Koh , Liang Hsia
IPC分类号： H01L29/772 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864
摘要： An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.
摘要翻译：从NMOS晶体管的栅极去除间隔物的示例性过程。在NMOS和PMOS晶体管和衬底上形成应力产生层。在一个实施例中，栅极上的间隔物被去除，使得应力层更靠近器件的通道。应力产生层优选为拉伸氮化物层。应力产生层优选为接触蚀刻停止衬层。在一个实施例中，栅极，源极和漏极区域在形成应力产生层之前具有硅化物层。该实施例改善了NMOS晶体管的性能。

78. 发明申请

US20060220110A1 INTEGRATED CIRCUIT WITH PROTECTED IMPLANTATION PROFILES AND METHOD FOR THE FORMATION THEREOF 有权
标题翻译：具有保护植入物种的集成电路及其形成方法
公开(公告)号：US20060220110A1
公开(公告)日：2006-10-05
申请号：US11421047
申请日：2006-05-30
申请人： Tommy Lai , Pradeep Yelehanka , Jia Zhen Zheng , Weining Li
发明人： Tommy Lai , Pradeep Yelehanka , Jia Zhen Zheng , Weining Li
IPC分类号： H01L29/792 , H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/31155 , H01L21/3144 , H01L27/1052 , H01L27/11546
摘要： An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.
摘要翻译：集成电路结构包括提供半导体衬底并在半导体衬底上形成至少一个氧化物 - 氮化物 - 氧化物电介质层。在形成氧化物 - 氮化物 - 氧化物电介质层之后，至少一个注入形成在氧化物 - 氮化物 - 氧化物介电层下方的半导体衬底的至少一个区域中。

79. 发明申请

US20060202343A1 Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication 有权
标题翻译：用于双重镶嵌制造中Cu阻挡层和蚀刻停止层的氧掺杂SiC
公开(公告)号：US20060202343A1
公开(公告)日：2006-09-14
申请号：US11410718
申请日：2006-04-25
申请人： Liu Huang , John Sudijono , Koh Wee
发明人： Liu Huang , John Sudijono , Koh Wee
IPC分类号： H01L23/52
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： A method of forming a dual damascene structure with improved performance is described. A first etch stop layer comprised of oxygen doped SiC is deposited on a SiC barrier layer to form a composite barrier/etch stop layer on a substrate. The remainder of the damascene stack is formed by sequentially depositing a first dielectric layer, a second oxygen doped SiC etch stop layer, and a second dielectric layer. A via and overlying trench are formed and filled with a diffusion barrier layer and a metal layer. The oxygen doped SiC layers have a lower dielectric constant than SiC or SiCN and a higher breakdown field than SiC. The etch selectivity of a C4F8/Ar etch for a SiCOH layer relative to the oxygen doped SiC layer is at least 6:1 because of a lower oxygen content in the oxygen doped SiC layer.
摘要翻译：描述了一种形成具有改进性能的双镶嵌结构的方法。由氧掺杂的SiC构成的第一蚀刻停止层沉积在SiC阻挡层上，以在衬底上形成复合势垒/蚀刻停止层。镶嵌层的剩余部分通过依次沉积第一介电层，第二氧掺杂的SiC蚀刻停止层和第二介电层而形成。形成通孔和上覆沟槽并填充有扩散阻挡层和金属层。氧掺杂的SiC层具有比SiC或SiCN更低的介电常数和比SiC更高的击穿场。对于SiCOH层，相对于氧掺杂的SiC层，C 4 Si 8 N / Ar蚀刻的蚀刻选择性至少为6:1，因为氧含量低氧掺杂的SiC层。

80. 发明申请

US20060180848A1 WING GATE TRANSISTOR FOR INTEGRATED CIRCUITS 有权
标题翻译：用于集成电路的栅极晶体管
公开(公告)号：US20060180848A1
公开(公告)日：2006-08-17
申请号：US11380378
申请日：2006-04-26
申请人： Timothy Phua , Kheng Chok Tee , Liang Choo Hsia
发明人： Timothy Phua , Kheng Chok Tee , Liang Choo Hsia
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/6653 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.
摘要翻译：提供一种用于形成半导体器件的系统。在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。盖材料和栅极材料的一部分被加工以形成盖和门体部分。门体部分上的翼部由栅极材料的剩余部分形成。栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

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