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61. 发明授权

US06225820B1 Semiconductor device having improved input buffer circuit 有权
标题翻译：具有改进的输入缓冲电路的半导体器件
公开(公告)号：US06225820B1
公开(公告)日：2001-05-01
申请号：US09383408
申请日：1999-08-26
申请人： Jae Woon Kim , Jung Yong Lee
发明人： Jae Woon Kim , Jung Yong Lee
IPC分类号： H03K19003
CPC分类号： H03K19/0027
摘要： An input buffer circuit for a semiconductor device includes a first input buffer unit having first and second transistors, a second input buffer unit coupled to the first input buffer unit, the second input buffer unit having third and fourth transistors, a control unit for activating one of the first and second input buffer units, and a switching unit having fifth, sixth, and seventh transistors and coupled to the control unit.
摘要翻译：一种用于半导体器件的输入缓冲器电路包括具有第一和第二晶体管的第一输入缓冲器单元，耦合到第一输入缓冲单元的第二输入缓冲单元，具有第三和第四晶体管的第二输入缓冲单元，用于激活一个的第一和第二输入缓冲器单元，以及具有第五，第六和第七晶体管的耦合到控制单元的开关单元。

62. 发明授权

US06831478B2 Open drain type output buffer 有权
标题翻译：开漏型输出缓冲器
公开(公告)号：US06831478B2
公开(公告)日：2004-12-14
申请号：US10425824
申请日：2003-04-30
申请人： Jung-Hwan Choi
发明人： Jung-Hwan Choi
IPC分类号： H03K19003
CPC分类号： H04L25/028 , H03K19/00323
摘要： The open-drain type output buffer includes a first driver and at east one of (1) at least one secondary driver and (2) at least one tertiary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary and tertiary drivers have first and second states. Each secondary and tertiary driver pulls the output node towards the low voltage when in the first state, and pulls the output node towards the low voltage in the second state. A control circuit, when a secondary driver is included, controls the secondary driver such that the secondary driver is in the second state when it has been determined that at least two consecutive low voltage output data have been generated. The control circuit, when a tertiary driver is included, controls the tertiary driver such that the tertiary driver is in the first state when a transition from a steady high voltage output data to a low voltage output data is determined.
摘要翻译：开漏型输出缓冲器包括第一驱动器，并且在（1）至少一个辅助驱动器的东侧和（2）至少一个第三驱动器的东一侧。第一个驱动器基于输入数据选择性地将输出节点拉向低电压。二级和三级驾驶员有第一和第二州。当处于第一状态时，每个次级和三级驱动器将输出节点拉向低电压，并且在第二状态下将输出节点拉向低电压。当包括次级驱动器时，控制电路控制次级驱动器，使得当已经确定已经生成了至少两个连续的低电压输出数据时，辅助驱动器处于第二状态。当包括三级驱动器时，控制电路控制第三驱动器，使得当确定从稳定的高电压输出数据到低电压输出数据的转变时，第三驱动器处于第一状态。

63. 发明授权

US06812731B1 Quintuple modular redundancy for high reliability circuits implemented in programmable logic devices 有权
标题翻译：用于在可编程逻辑器件中实现的高可靠性电路的五元组冗余
公开(公告)号：US06812731B1
公开(公告)日：2004-11-02
申请号：US10787348
申请日：2004-02-26
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H03K19003
CPC分类号： H03K19/00392 , G06F17/5054 , H03K19/17736 , H03K19/17764
摘要： Structures and methods for generating high reliability designs for PLDs on which single event upsets have minimal impact. When standard triple modular redundancy (TMR) methods are used in PLDs, a single event upset can short together two module output signals and render two of the three voting circuit input signals invalid. The invention addresses this issue by providing quintuple modular redundancy (QMR) for high-reliability circuits implemented in PLDs. Thus, a single event upset that inadvertently shorts together two PLD interconnect lines can render invalid only two out of five module output signals. The majority of the five modules still provide the correct value, and the voting circuit is able to correctly resolve the error. In some embodiments, a user selects a high-reliability circuit implementation option and/or a PLD particularly suited to a QMR implementation, and the PLD implementation software automatically implements the QMR structure for the user circuit.
摘要翻译：用于为PLD生成高可靠性设计的结构和方法，其中单个事件的影响具有最小的影响。当在PLD中使用标准的三重模块冗余（TMR）方法时，单个事件的不适可以将两个模块输出信号缩短，并使三个投票电路输入信号中的两个无效。本发明通过为在PLD中实现的高可靠性电路提供五元组冗余（QMR）来解决这个问题。因此，单独的事件不适，无意中将两个PLD互连线组合在一起，可能只能使五个模块输出信号中的两个变为无效。五个模块中的大多数仍然提供正确的值，并且投票电路能够正确地解决错误。在一些实施例中，用户选择特别适合于QMR实现的高可靠性电路实现选项和/或PLD，并且PLD实现软件自动实现用户电路的QMR结构。

64. 发明授权

US06806729B2 Ground bounce detection circuit for use in data error reduction 有权
标题翻译：用于数据误差降低的地面反弹检测电路
公开(公告)号：US06806729B2
公开(公告)日：2004-10-19
申请号：US09766204
申请日：2001-01-19
申请人： Douglas Elmer Wallace, Jr. , James Bryce Mobley
发明人： Douglas Elmer Wallace, Jr. , James Bryce Mobley
IPC分类号： H03K19003
CPC分类号： H03K19/00346
摘要： A circuit for detecting ground bounce and for using the detection information to reduce data error resulting therefrom is described. In one embodiment an on-chip ground bounce detector circuit detects large ground bounce events caused by the simultaneous switching of I/O buffers of the chip and notifies an on-chip logic circuit of the event The on-chip logic circuit can be implemented to take a variety of actions upon receipt of notification from the detection circuit that a ground bounce has been detected.
摘要翻译：描述用于检测接地反弹的电路和用于使用检测信息来减少由此产生的数据误差的电路。在一个实施例中，片上地面反弹检测器电路检测由芯片的I / O缓冲器的同时切换引起的大的地面反弹事件，并将片上逻辑电路通知事件。片上逻辑电路可以被实现为在从检测电路接收到已经检测到地面反弹的通知时采取各种动作。

65. 发明授权

US06794894B2 Method and system for bidirectional signal transmission 有权
标题翻译：双向信号传输的方法和系统
公开(公告)号：US06794894B2
公开(公告)日：2004-09-21
申请号：US10178252
申请日：2002-06-24
申请人： Aaron Nygren
发明人： Aaron Nygren
IPC分类号： H03K19003
CPC分类号： H04L25/028 , H04L5/1423 , H04L25/026 , H04L25/0278 , H04L25/0298
摘要： A system for bidirectional signal transmission of an electrical signal from a transmitter at a first location to a receiver at a second location, and from a transmitter at the second location to a receiver at the first location via a common transmission line forms, with each receiver, a line termination for matching the received electrical signal. Each transmitter is in the form of a combined transmission/termination circuit configuration which may in each case be operated in a transmission operating mode and in a reception/termination operating mode. A control circuit produces an operating mode control signal. Each transmission/termination circuit configuration is configured such that it can be switched either to the transmission operating mode or to the reception/termination operating mode depending on the operating mode control signal which is supplied from the control circuit. A method for bidirectional signal transmission of an electrical signal is also provided.
摘要翻译：用于将电信号从第一位置处的发射机到第二位置处的接收机以及从第二位置处的发射机经由公共传输线向第一位置的接收机双向信号传输的系统与每个接收机用于匹配所接收的电信号的线路终端。每个发射机是组合的传输/终端电路配置的形式，其可以在每种情况下以传输操作模式和接收/终止操作模式操作。控制电路产生工作模式控制信号。每个发送/终端电路配置被配置为使得其可以根据从控制电路提供的操作模式控制信号切换到传输操作模式或接收/终止操作模式。还提供了一种用于电信号的双向信号传输的方法。

66. 发明授权

US06765406B2 Circuit board configured to provide multiple interfaces 失效
标题翻译：电路板配置为提供多个接口
公开(公告)号：US06765406B2
公开(公告)日：2004-07-20
申请号：US10330821
申请日：2002-12-27
申请人： Ji Eun Jang , Jae Jin Lee
发明人： Ji Eun Jang , Jae Jin Lee
IPC分类号： H03K19003
CPC分类号： H05K1/0246 , G11C7/10 , G11C11/4093 , H03K19/0175 , H05K1/0286 , H05K1/14 , H05K1/141 , H05K2201/044 , H05K2201/10022
摘要： A circuit board configured to provide multiple interfaces is disclosed. The circuit board comprises a termination slot inserted with a termination module configured to modulate circuits by applying a termination resistance and a termination voltage. If the termination module is inserted into the termination slot, the circuit board operates as a series stub terminated transceiver logic (SSTL) interface. Otherwise, the board operates as a low voltage transistor logic (LVTTL) interface. Additionally, the board comprises a switch configured to selectively connect a termination resistance to a bus. If the switch connects the termination resistance to the bus, the board operates as an SSTL interface. Otherwise, the board operates as an LVTTL interface.
摘要翻译：公开了一种被配置为提供多个接口的电路板。电路板包括插入有终端模块的终端插槽，其配置成通过施加终端电阻和终止电压来调制电路。如果终端模块插入终端插槽，则电路板作为串行存根终端收发器逻辑（SSTL）接口运行。否则，该板作为低电压晶体管逻辑（LVTTL）接口工作。另外，电路板包括被配置为选择性地将终端电阻连接到总线的开关。如果开关将终端电阻连接到总线，则该板作为SSTL接口工作。否则，该板作为LVTTL接口运行。

67. 发明授权

US06756808B2 Clock edge detection circuit 有权
标题翻译：时钟边缘检测电路
公开(公告)号：US06756808B2
公开(公告)日：2004-06-29
申请号：US10145565
申请日：2002-05-14
申请人： Yasunari Furuya
发明人： Yasunari Furuya
IPC分类号： H03K19003
CPC分类号： H03K5/26
摘要： The clock edge detection circuit is equipped with a first delay circuit 11 that delays a first clock signal and outputs a first delay clock signal, a second delay circuit 21 that delays a second clock signal and outputs a second delay clock signal, a first retaining circuit 12 that retains a level of the first delay clock signal at an edge of the second clock signal, a second retaining circuit 22 that retains a level of the first clock signal at an edge of the second delay clock signal, and a logical circuit 13 that outputs, based on the output signals of the first and second retaining circuits, a detection signal representing whether or not an edge of the first clock signal and an edge of the second clock signal are within a predetermined time range.
摘要翻译：时钟沿检测电路配备有延迟第一时钟信号并输出第一延迟时钟信号的第一延迟电路11，延迟第二时钟信号并输出第二延迟时钟信号的第二延迟电路21，第一保持电路 12，其在第二时钟信号的边缘处保持第一延迟时钟信号的电平;第二保持电路22，其将第一时钟信号的电平保持在第二延迟时钟信号的边沿;以及逻辑电路13，基于第一和第二保持电路的输出信号输出表示第一时钟信号的边沿和第二时钟信号的边沿是否在预定时间范围内的检测信号。

68. 发明授权

US06747475B2 Method and apparatus for driving a signal using switchable on-die termination 失效
标题翻译：使用可切换的片上端接驱动信号的方法和装置
公开(公告)号：US06747475B2
公开(公告)日：2004-06-08
申请号：US10024119
申请日：2001-12-17
申请人： Marcelo Yuffe , Zelig Wayner , Noam Yosef
发明人： Marcelo Yuffe , Zelig Wayner , Noam Yosef
IPC分类号： H03K19003
CPC分类号： H04L25/028 , G06F13/4072 , G06F13/4086 , H04L25/0278 , H04L25/0292
摘要： A circuit for driving and receiving signals on a bus line includes a pull-up switch and a pull-down switch. The pull-up switch has an impedance that matches the characteristic impedance of the bus line. The pull-down switch has an impedance of about half of the characteristic impedance of the bus line. When the circuit is receiving a signal or driving a logic high signal on the bus line, the pull-up switch is enabled so that the bus line voltage is pulled up, while the pull-down switch is disabled to prevent the pull-down switch from pulling down the bus line voltage. When the circuit is driving a logic low signal on the bus line, the pull-down switch is enabled so that the bus line voltage is pulled down, while the pull-up switch is disabled to prevent the pull-up switch from pulling up the bus line voltage.
摘要翻译：用于在总线上驱动和接收信号的电路包括上拉开关和下拉开关。上拉开关具有与总线线路的特性阻抗匹配的阻抗。下拉开关的阻抗约为总线特性阻抗的一半。当电路在总线上接收信号或驱动逻辑高电平信号时，使能上拉开关，使总线电压上拉，同时禁用下拉开关以防止下拉开关从下拉母线电压。当电路驱动总线上的逻辑低电平信号时，下拉开关被使能，使得总线电压被拉低，而上拉开关被禁止，以防止上拉开关向上拉总线电压。

69. 发明授权

US06737885B1 Integrated circuit devices with power supply detection circuitry 有权
标题翻译：具有电源检测电路的集成电路器件
公开(公告)号：US06737885B1
公开(公告)日：2004-05-18
申请号：US10327284
申请日：2002-12-20
申请人： Sergey Y. Shumarayev , Thomas H. White
发明人： Sergey Y. Shumarayev , Thomas H. White
IPC分类号： H03K19003
CPC分类号： H03K17/22 , G06F1/24 , G06F1/28
摘要： Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.
摘要翻译：提供集成电路装置，其包括指示电源是否达到功能电压电平的功率检测电路。功率检测电路包括耦合到电源的锁存器，其可以检测所有电源是否已经达到功能电压电平，逻辑电路以提供适当的输出信号，以及向电力检测电路提供电流的阱偏置电路。良好的偏置电路提供来自第一电源的电流以达到功能电压电平，使得可以从功率检测电路提供指示，而不需要所有电源的功能电压电平。来自功率检测电路的输出可以与控制信号组合，用于各种应用。应用包括将集成电路器件置于复位状态，直到电源达到功能电压电平。

70. 发明授权

US06714039B2 Internal bus termination technique for integrated circuits with local process/voltage/temperature compensation 有权
标题翻译：具有局部过程/电压/温度补偿的集成电路的内部总线终端技术
公开(公告)号：US06714039B2
公开(公告)日：2004-03-30
申请号：US10144112
申请日：2002-05-13
申请人： Manuel Salcido , Gilbert Yoh , Salvador Salcido, Jr. , Scott T. Evans
发明人： Manuel Salcido , Gilbert Yoh , Salvador Salcido, Jr. , Scott T. Evans
IPC分类号： H03K19003
CPC分类号： G06F13/4086
摘要： An active termination technique for reducing the propagation delay of a signal across a transmission line is presented. In accordance with a preferred embodiment of the invention, repeaters along a transmission line are paired with active termination circuits in very close proximity to the repeater in order to prevent signal reflections caused by the repeaters. The repeaters and associated active termination circuits are implemented with at least one PFET and at least one NFET, each having the same transistor gate lengths. The PFETs and the NFETs in the repeater and associated termination are ratioed to vary similarly over process/voltage/temperature variation.
摘要翻译：提出了一种用于减少跨越传输线的信号的传播延迟的主动终止技术。根据本发明的优选实施例，沿着传输线的中继器与非常接近中继器的有源终端电路配对，以便防止由中继器引起的信号反射。中继器和相关的有源终端电路用至少一个PFET和至少一个NFET实现，每个NFET具有相同的晶体管栅极长度。中继器和相关终端中的PFET和NFET的比值与过程/电压/温度变化相似。

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