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1. 发明授权

US06747475B2 Method and apparatus for driving a signal using switchable on-die termination 失效
标题翻译：使用可切换的片上端接驱动信号的方法和装置
公开(公告)号：US06747475B2
公开(公告)日：2004-06-08
申请号：US10024119
申请日：2001-12-17
申请人： Marcelo Yuffe , Zelig Wayner , Noam Yosef
发明人： Marcelo Yuffe , Zelig Wayner , Noam Yosef
IPC分类号： H03K19003
CPC分类号： H04L25/028 , G06F13/4072 , G06F13/4086 , H04L25/0278 , H04L25/0292
摘要： A circuit for driving and receiving signals on a bus line includes a pull-up switch and a pull-down switch. The pull-up switch has an impedance that matches the characteristic impedance of the bus line. The pull-down switch has an impedance of about half of the characteristic impedance of the bus line. When the circuit is receiving a signal or driving a logic high signal on the bus line, the pull-up switch is enabled so that the bus line voltage is pulled up, while the pull-down switch is disabled to prevent the pull-down switch from pulling down the bus line voltage. When the circuit is driving a logic low signal on the bus line, the pull-down switch is enabled so that the bus line voltage is pulled down, while the pull-up switch is disabled to prevent the pull-up switch from pulling up the bus line voltage.
摘要翻译：用于在总线上驱动和接收信号的电路包括上拉开关和下拉开关。上拉开关具有与总线线路的特性阻抗匹配的阻抗。下拉开关的阻抗约为总线特性阻抗的一半。当电路在总线上接收信号或驱动逻辑高电平信号时，使能上拉开关，使总线电压上拉，同时禁用下拉开关以防止下拉开关从下拉母线电压。当电路驱动总线上的逻辑低电平信号时，下拉开关被使能，使得总线电压被拉低，而上拉开关被禁止，以防止上拉开关向上拉总线电压。

2. 发明授权

US06842035B2 Apparatus and method for bus signal termination compensation during detected quiet cycle 有权
标题翻译：在检测到的安静周期期间总线信号终端补偿的装置和方法
公开(公告)号：US06842035B2
公开(公告)日：2005-01-11
申请号：US10335032
申请日：2002-12-31
申请人： Tsvika Kurts , Zelig Wayner , Tommy Bojan
发明人： Tsvika Kurts , Zelig Wayner , Tommy Bojan
IPC分类号： H03K17/16 , H04L25/02 , H03K19/003
CPC分类号： H04L25/0278 , H03K17/164
摘要： A value to better match a termination circuit to a characteristic impedance of a bus signal line is determined. A determination is also made as to when a bus, that includes the line and that is being used by a bus agent in its normal mode of operation, will be available for adjusting the termination circuit in a Quiet Cycle, based at least on knowledge of the bus protocol and tracking of certain bus protocol events. The termination circuit is adjusted according to the determined value, during the Quiet Cycle.
摘要翻译：确定将终端电路更好地匹配总线信号线的特性阻抗的值。还决定了当总线（包括线路，正在由其正常工作模式使用的总线）将可用于在安静周期中调整终端电路时，至少基于以下知识：总线协议和跟踪某些总线协议事件。在安静周期期间，根据确定的值调节终端电路。

3. 发明授权

US07536485B2 Processor having inactive state of operation and method thereof 有权
标题翻译：具有无效操作状态的处理器及其方法
公开(公告)号：US07536485B2
公开(公告)日：2009-05-19
申请号：US11319805
申请日：2005-12-29
申请人： Gila Kamhi , Zelig Wayner , Amit Gradstein , Yoad Yagil , Thierry Pons , Ittai Anati , Ranan Fraer
发明人： Gila Kamhi , Zelig Wayner , Amit Gradstein , Yoad Yagil , Thierry Pons , Ittai Anati , Ranan Fraer
IPC分类号： G06F13/10 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： Embodiments of the present invention provide a processor having an inactive state of operation and methods thereof. The processor, according to some demonstrative embodiments of the invention, the processor may include a controller to determine an inactive state of operation is to be entered, and to cause a predetermined set of one or more execution units to execute a predetermined sequence of one or more micro-operations prior to entering the inactive state. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供一种具有非活动状态的处理器及其方法。根据本发明的一些演示实施例的处理器，处理器可以包括用于确定要进入的不活动状态的控制器，并且使一个或多个执行单元的预定集合执行预定的一个或多个进入非活动状态之前的更多微操作。描述和要求保护其他实施例。

4. 发明授权

US6031393A Pass gate input buffer for a mixed voltage environment 失效
标题翻译：用于混合电压环境的通过门极输入缓冲器
公开(公告)号：US6031393A
公开(公告)日：2000-02-29
申请号：US1506
申请日：1997-12-31
申请人： Zelig Wayner
发明人： Zelig Wayner
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00315
摘要： An input buffer to interface among devices on a main circuit board is described. The input buffer includes a first transistor coupled between a first terminal and an input terminal of an inverter. The first transistor has an enable terminal adapted to be coupled to a first voltage supply. A second transistor that is coupled between the first terminal and the input terminal is also included. The input buffer further includes a control circuit to enable the second transistor. The control circuit is coupled to the first terminal, an enable terminal of the second transistor, the input terminal, and an output terminal of the inverter. A method for buffering signals among devices on a main circuit board comprises receiving a first signal in a first state from a first device. A first portion of the first signal is transmitted through a first transistor. A second portion of the first signal is transmitted through a second transistor. A second signal is generated by applying the first signal to the enable terminals of the third and fourth transistors. The second signal is then transmitted to a second device.
摘要翻译：描述了用于在主电路板上的设备之间进行接口的输入缓冲器。输入缓冲器包括耦合在第一端子和反相器的输入端子之间的第一晶体管。第一晶体管具有适于耦合到第一电压源的使能端子。还包括耦合在第一端子和输入端子之间的第二晶体管。输入缓冲器还包括用于使第二晶体管启动的控制电路。控制电路耦合到第一端子，第二晶体管的使能端子，输入端子和反相器的输出端子。用于在主电路板上的设备之间缓冲信号的方法包括从第一设备接收处于第一状态的第一信号。第一信号的第一部分通过第一晶体管传输。第一信号的第二部分通过第二晶体管传输。通过将第一信号施加到第三和第四晶体管的使能端来产生第二信号。然后将第二信号发送到第二设备。

5. 发明申请

US20070174589A1 Processor having inactive state of operation and method thereof 有权
标题翻译：具有无效操作状态的处理器及其方法
公开(公告)号：US20070174589A1
公开(公告)日：2007-07-26
申请号：US11319805
申请日：2005-12-29
申请人： Gila Kamhi , Zelig Wayner , Amit Gradstein , Yoad Yagil , Thierry Pons , Ittai Anati , Ranan Fraer
发明人： Gila Kamhi , Zelig Wayner , Amit Gradstein , Yoad Yagil , Thierry Pons , Ittai Anati , Ranan Fraer
IPC分类号： G06F9/30
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： Embodiments of the present invention provide a processor having an inactive state of operation and methods thereof. The processor, according to some demonstrative embodiments of the invention, the processor may include a controller to determine an inactive state of operation is to be entered, and to cause a predetermined set of one or more execution units to execute a predetermined sequence of one or more micro-operations prior to entering the inactive state. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供一种具有非活动状态的处理器及其方法。根据本发明的一些演示实施例的处理器，处理器可以包括用于确定要进入的不活动状态的控制器，并且使一个或多个执行单元的预定集合执行预定的一个或多个进入非活动状态之前的更多微操作。描述和要求保护其他实施例。

6. 发明授权

US6084430A Input buffer for a mixed voltage environment 失效
标题翻译：用于混合电压环境的输入缓冲器
公开(公告)号：US6084430A
公开(公告)日：2000-07-04
申请号：US2232
申请日：1997-12-31
申请人： Zelig Wayner
发明人： Zelig Wayner
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00315
摘要： An input buffer to interface between a main logic circuit and a peripheral device, which includes a first transistor that is adapted to be coupled to a first voltage supply and a first terminal, is described. A second transistor, which is adapted to be coupled to a second voltage supply and said terminal, is also included. The input buffer includes a first logic circuit to limit the amount of voltage applied to the first and second enable terminals of the first and second transistors. The first logic circuit is adapted to be coupled to a second terminal, the first enable terminal, and the second enable terminal. A second logic circuit, designed to limit the amount of voltage applied to the first terminal, is also included. The second logic circuit is coupled to the input terminals of the first and second transistors, as well as the first terminal. A method for buffering a signal received from a peripheral component includes receiving a first signal from a peripheral component. The voltage level of the first signal is reduced, and it is applied to the enable terminals of a first and a second transistor. A second signal is applied to an output terminal, and the voltage level of the second signal is limited. The second signal is then transmitted to an internal component.
摘要翻译：描述了一种用于在主逻辑电路和外围设备之间进行接口的输入缓冲器，其包括适于耦合到第一电压源和第一端子的第一晶体管。还包括适于耦合到第二电压源和所述端子的第二晶体管。输入缓冲器包括第一逻辑电路，用于限制施加到第一和第二晶体管的第一和第二使能端的电压量。第一逻辑电路适于耦合到第二终端，第一使能终端和第二使能终端。还包括设计用于限制施加到第一端子的电压量的第二逻辑电路。第二逻辑电路耦合到第一和第二晶体管的输入端以及第一端。用于缓冲从外围组件接收的信号的方法包括从外围组件接收第一信号。降低第一信号的电压电平，并施加到第一和第二晶体管的使能端。第二信号被施加到输出端子，并且第二信号的电压电平受到限制。然后将第二信号发送到内部组件。

7. 发明授权

US6054875A Output buffer for a mixed voltage environment 失效
标题翻译：用于混合电压环境的输出缓冲器
公开(公告)号：US6054875A
公开(公告)日：2000-04-25
申请号：US1764
申请日：1997-12-31
申请人： Zelig Wayner
发明人： Zelig Wayner
IPC分类号： H03K19/003 , H03K17/16 , H03B1/00 , H03K19/0175
CPC分类号： H03K19/00315
摘要： An output buffer to serve as an interface between a main logic circuit and a peripheral device is described. The output buffer includes a first transistor adapted to be coupled to a first voltage supply and an output terminal. The first transistor is designed to charge the output terminal to a first state. A pull-down network to charge the output terminal to a second state is also included. The pull-down network is adapted to be coupled between the output terminal and a second voltage supply and is designed for alternate operation with the first transistor. The output buffer also includes a logic circuit to enable the first transistor and the pull-down network. The logic circuit is coupled to an enable terminal of the first transistor, the pull-down network, the first voltage supply, and the second voltage supply.
摘要翻译：描述了用作主逻辑电路和外围设备之间的接口的输出缓冲器。输出缓冲器包括适于耦合到第一电压源和输出端的第一晶体管。第一晶体管被设计成将输出端子充电到第一状态。还包括将输出端子充电到第二状态的下拉网络。下拉网络适于耦合在输出端子和第二电压源之间，并被设计为与第一晶体管交替工作。输出缓冲器还包括使第一晶体管和下拉网络能够实现的逻辑电路。逻辑电路耦合到第一晶体管的使能端，下拉网络，第一电压源和第二电压源。

8. 发明授权

US07227377B2 Apparatus and method for bus signal termination compensation during detected quiet cycle 有权
标题翻译：在检测到的安静周期期间总线信号终端补偿的装置和方法
公开(公告)号：US07227377B2
公开(公告)日：2007-06-05
申请号：US11026651
申请日：2004-12-31
申请人： Tsvika Kurts , Zelig Wayner , Tommy Bojan
发明人： Tsvika Kurts , Zelig Wayner , Tommy Bojan
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H03K17/164
摘要： A value to better match a termination circuit to a characteristic impedance of a bus signal line is determined. A determination is also made as to when a bus, that includes the line and that is being used by a bus agent in its normal mode of operation, will be available for adjusting the termination circuit in a Quiet Cycle, based at least on knowledge of the bus protocol and tracking of certain bus protocol events. The termination circuit is adjusted according to the determined value, during the Quiet Cycle.
摘要翻译：确定将终端电路更好地匹配总线信号线的特性阻抗的值。还决定了当总线（包括线路，正在由其正常工作模式使用的总线）将可用于在安静周期中调整终端电路时，至少基于以下知识：总线协议和跟踪某些总线协议事件。在安静周期期间，根据确定的值调节终端电路。

9. 发明申请

US20050151562A1 Apparatus and method for bus signal termination compensation during detected quiet cycle 有权
公开(公告)号：US20050151562A1
公开(公告)日：2005-07-14
申请号：US11026651
申请日：2004-12-31
申请人： Tsvika Kurts , Zelig Wayner , Tommy Bojan
发明人： Tsvika Kurts , Zelig Wayner , Tommy Bojan
IPC分类号： H03K17/16 , H04L25/02
CPC分类号： H04L25/0278 , H03K17/164
摘要： A value to better match a termination circuit to a characteristic impedance of a bus signal line is determined. A determination is also made as to when a bus, that includes the line and that is being used by a bus agent in its normal mode of operation, will be available for adjusting the termination circuit in a Quiet Cycle, based at least on knowledge of the bus protocol and tracking of certain bus protocol events. The termination circuit is adjusted according to the determined value, during the Quiet Cycle.

10. 发明申请

US20050083095A1 Adaptive input/output buffer and methods thereof 审中-公开
标题翻译：自适应输入/输出缓冲器及其方法
公开(公告)号：US20050083095A1
公开(公告)日：2005-04-21
申请号：US10685418
申请日：2003-10-16
申请人： Tsvika Kurts , Zelig Wayner
发明人： Tsvika Kurts , Zelig Wayner
IPC分类号： G06F13/16 , G06F13/40 , H03H11/26
CPC分类号： G06F13/4059
摘要： A controller having programmable delay cells in its input/output channels may also include respective registers storing digital values that control the time delays introduced by the respective delay cells. The values programmed to the registers may be determined by testing the timing of signals between the controller and one or more devices coupled to the channels. The tests may include setting the registers with test values from a set of sequential test values, driving a particular pattern on the signals from the controller to the one or more devices, and checking whether portions of the pattern are received accurately by the one or more devices. Adjusting the timing of the signals may involve centering of the signals with respect to set up and hold time restrictions.
摘要翻译：在其输入/输出通道中具有可编程延迟单元的控制器还可以包括存储数字值的各个寄存器，这些数字值控制各个延迟单元引入的时间延迟。编程到寄存器的值可以通过测试控制器与耦合到通道的一个或多个设备之间的信号的定时来确定。这些测试可以包括用来自一组顺序测试值的测试值来设置寄存器，驱动来自控制器的信号到一个或多个设备的特定模式，以及检查模式的部分是否被一个或多个设备。调整信号的时序可能包括相对于建立和保持时间限制的信号的中心。

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