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61. 发明申请

US20060227629A1 Memory device and control method therefor 有权
标题翻译：存储器及其控制方法
公开(公告)号：US20060227629A1
公开(公告)日：2006-10-12
申请号：US11378444
申请日：2006-03-16
申请人： Koji Shimbayashi , Takaaki Furuyama , Kenji Shibata
发明人： Koji Shimbayashi , Takaaki Furuyama , Kenji Shibata
IPC分类号： G11C7/06
CPC分类号： G11C7/08 , G11C7/1018 , G11C16/26 , G11C16/32
摘要： An access identification circuit (4) identifies a first access operation or a second access operation and outputs an identification signal S. During the first access operation, stored data is read out after detecting a column address CADD, a burst address, and updating a word line to newly select memory cells MC. In the second access operation, the memory cells MC connected to the common word line which has been selected are selected by sequentially switching column selector switches. Operating condition information Dx (DAx and/or DBx) used for setting a load condition in a dummy load circuit (5) and/or setting a pulse width for an equalize signal EQ in an amplification control circuit (6) is stored in each of first and second storage sections (1, 2) that are provided for the first and second access operations, respectively. The operating condition information Dx is selected by a selector circuit (3) in response to the identification signal S and fed to the dummy load circuit (5) and/or the amplification control circuit (6). A suitable operating condition is selected for each of the access operations.
摘要翻译：访问识别电路（4）识别第一访问操作或第二访问操作并输出识别信号S.在第一访问操作期间，在检测列地址CADD，突发地址和更新字之后读出存储的数据行新选择存储单元MC。在第二访问操作中，通过依次切换列选择器开关来选择连接到所选择的公共字线的存储单元MC。在放大控制电路（6）中用于设置虚拟负载电路（5）中的负载条件和/或设定均衡信号EQ的脉冲宽度的工作条件信息Dx（DAx和/或DBx）被存储在分别为第一和第二存取操作提供的第一和第二存储部分（1,2）。操作条件信息Dx由选择器电路（3）响应于识别信号S选择并馈送到虚拟负载电路（5）和/或放大控制电路（6）。为每个访问操作选择合适的操作条件。

62. 发明申请

US20060171218A1 Semiconductor memory device having N-bit prefetch type and method of transferring data thereof 有权
标题翻译：具有N位预取类型的半导体存储器件及其数据传送方法
公开(公告)号：US20060171218A1
公开(公告)日：2006-08-03
申请号：US11148231
申请日：2005-06-09
申请人： Jun Chun
发明人： Jun Chun
IPC分类号： G11C29/00
CPC分类号： G11C7/12 , G11C7/1018 , G11C11/4094
摘要： A semiconductor memory device in which only global I/O buses, which receive one or more data groups that must be output first among a N number of data groups that are prefetched in a N-bit prefetch type, from an array of memory cells are precharged with a ½ power supply voltage, thereby making the output speed of the data groups that must be output first thing faster than that of the remaining data groups. The semiconductor memory device includes a data bus controller for precharging predetermined data buses that receive one or more data group that must be output to the outside first among a N number of data groups that are prefetched in a N-bit prefetch type from an array of memory cells, using information to decide an I/O sequence of the N number of the data groups.
摘要翻译：一种半导体存储器件，其中仅存储一个或多个数据组的全局I / O总线，所述I / O总线从存储器单元阵列接收在N个预取类型中预取的N个数据组中必须首先输出的一个或多个数据组，用1/2电源电压预充电，从而使必须输出的数据组的输出速度比其余数据组的输出速度快。半导体存储器件包括一个数据总线控制器，用于预先接收预定数据总线，该数据总线接收一个或多个数据组，该数据组必须首先从N位预取类型中预取的N个数据组中输出，使用信息来决定N个数据组的I / O序列。

63. 发明授权

US07057959B2 Semiconductor memory having mode register access in burst mode 有权
标题翻译：半导体存储器在突发模式下具有模式寄存器访问
公开(公告)号：US07057959B2
公开(公告)日：2006-06-06
申请号：US11001619
申请日：2004-12-02
申请人： Shinya Fujioka , Shinichi Yamada , Kotoku Sato , Jun Ohno
发明人： Shinya Fujioka , Shinichi Yamada , Kotoku Sato , Jun Ohno
IPC分类号： G11C7/22 , G11C5/14
CPC分类号： G11C7/1018 , G11C7/22 , G11C2207/2227
摘要： A method for controlling a semiconductor memory in which a mode register can be set in a burst mode. To set an operation mode in the burst mode, the semiconductor memory is changed first from the burst mode, through a power-down mode, to a standby mode of non-burst mode. Then the semiconductor memory is changed to a mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.
摘要翻译：一种用于控制其中可以以突发模式设置模式寄存器的半导体存储器的方法。为了在突发模式下设置操作模式，首先将半导体存储器从突发模式通过掉电模式改变为非突发模式的待机模式。然后，当以与非突发模式中使用的相同的预定顺序输入命令时，半导体存储器被改变为模式寄存器设置模式以设置模式寄存器。

64. 发明授权

US07051178B2 Burst write in a non-volatile memory device 有权
标题翻译：突发写入非易失性存储设备
公开(公告)号：US07051178B2
公开(公告)日：2006-05-23
申请号：US10747416
申请日：2003-12-29
申请人： Frankie F. Roohparvar
发明人： Frankie F. Roohparvar
IPC分类号： G06F12/00
CPC分类号： G11C7/1027 , G11C7/1018 , G11C7/1072 , G11C16/10 , G11C16/22 , G11C16/26 , G11C16/32
摘要： A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of rows and columns. During a read operation, a row of the memory array can be accessed and data written to a group of columns during a burst write operation. The burst columns are generated using an internal counter and an externally provided start address. Repeating sequences of commands and data packets are provided to the memory device. An externally provided data mask signal is used to write one of the data packets to the memory on each of the sequences.
摘要翻译：已经描述了包括非易失性存储器单元阵列的同步闪存。存储器件具有与SDRAM兼容的封装配置。同步闪速存储器件包括排列成多个行和列的非易失性存储单元阵列。在读取操作期间，可以访问存储器阵列的一行并且在突发写入操作期间将数据写入一组列。脉冲串列使用内部计数器和外部提供的起始地址生成。命令和数据包的重复序列被提供给存储器件。外部提供的数据掩码信号用于将每个数据包中的一个数据包写入每个序列上的存储器。

65. 发明授权

US07038966B2 Memory device and method having data path with multiple prefetch I/O configurations 失效
公开(公告)号：US07038966B2
公开(公告)日：2006-05-02
申请号：US11030844
申请日：2005-01-07
申请人： Brent Keeth , Brian Johnson , Troy A. Manning
发明人： Brent Keeth , Brian Johnson , Troy A. Manning
IPC分类号： G11C7/00
CPC分类号： G11C7/1072 , G11C7/1006 , G11C7/1018 , G11C7/1027 , G11C7/1045 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

66. 发明申请

US20060082478A1 Memory device and method having data path with multiple prefetch I/O configurations 有权
公开(公告)号：US20060082478A1
公开(公告)日：2006-04-20
申请号：US11284498
申请日：2005-11-21
申请人： Brent Keeth , Brian Johnson , Troy Manning
发明人： Brent Keeth , Brian Johnson , Troy Manning
IPC分类号： H03M9/00
CPC分类号： G11C7/1072 , G11C7/1006 , G11C7/1018 , G11C7/1027 , G11C7/1045 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

67. 发明授权

US06992944B2 Semiconductor memory device with reduced power consumption for refresh operation 失效
标题翻译：半导体存储器件具有降低功耗的刷新操作
公开(公告)号：US06992944B2
公开(公告)日：2006-01-31
申请号：US11079427
申请日：2005-03-15
申请人： Masato Takita , Kuninori Kawabata
发明人： Masato Takita , Kuninori Kawabata
IPC分类号： G11C7/00
CPC分类号： G11C7/1018 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4087
摘要： A semiconductor memory device includes a plurality of word decoders arranged in a plurality of columns, a plurality of word line selecting shift registers corresponding to the respective word decoders to indicate a word line subjected to refresh operation, and a shift control signal generating circuit operable to supply a shift control signal indicative of timing of shift operations to the plurality of word line selecting shift registers, wherein the said shift control signal generating circuit is configured to supply the shift control signal only to a column currently subjected to refresh operation among the plurality of columns.
摘要翻译：一种半导体存储器件，包括多列布置的多个字解码器，多个字线选择移位寄存器，其对应于各个字解码器，以指示经受刷新操作的字线;以及移位控制信号发生电路，向多个字线选择移位寄存器提供表示移位操作定时的移位控制信号，其中所述移位控制信号发生电路被配置为仅将移位控制信号提供给多个字线选择移位寄存器中当前经历刷新操作的列列。

68. 发明授权

US06992943B2 System and method for performing partial array self-refresh operation in a semiconductor memory device 有权
公开(公告)号：US06992943B2
公开(公告)日：2006-01-31
申请号：US10959804
申请日：2004-10-06
申请人： Hyong-Ryol Hwang , Jong-Hyun Choi , Hyun-Soon Jang
发明人： Hyong-Ryol Hwang , Jong-Hyun Choi , Hyun-Soon Jang
IPC分类号： G11C7/00
CPC分类号： G11C11/40622 , G11C7/1018 , G11C11/406 , G11C11/4087
摘要： Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or 1/16) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

69. 发明申请

US20050275470A1 Low power and low timing jitter phase-lock loop and method 失效
标题翻译：低功耗和低定时抖动锁相环和方法
公开(公告)号：US20050275470A1
公开(公告)日：2005-12-15
申请号：US10868284
申请日：2004-06-14
申请人： Dong Choi
发明人： Dong Choi
IPC分类号： G06F1/04 , H03L7/00 , H03L7/099
CPC分类号： G06F1/04 , G11C7/02 , G11C7/1006 , G11C7/1018 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/406 , G11C11/4076 , G11C11/4093 , H03L7/0891 , H03L7/0995 , H03L7/16 , H03L2207/10
摘要： A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.
摘要翻译：锁相环从输入时钟信号产生输出时钟信号。输出时钟信号通过时钟树耦合并被反馈到相位检测器，该相位检测器将输出时钟信号的相位与输入时钟信号的相位进行比较。输出时钟信号由具有耦合以接收来自相位检测器的输出的控制输入的压控振荡器和耦合到压控振荡器的输出的倍频器产生。结果，由倍频器产生的CLKOUT信号具有相对高的频率，而压控振荡器通过以较低的频率运行使用相对较小的功率。

70. 发明授权

US06930951B2 Semiconductor memory device capable of accessing data in continuous burst mode regardless of location of accessed data 有权
标题翻译：能够以连续脉冲串模式访问数据而不管访问数据的位置如何的半导体存储器件
公开(公告)号：US06930951B2
公开(公告)日：2005-08-16
申请号：US10744322
申请日：2003-12-22
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Jae-Bum Ko , Se-Jun Kim
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G11C8/08 , G11C7/10 , G11C8/00 , G11C8/12
CPC分类号： G11C7/1018
摘要： There is provided a semiconductor memory device and a method for driving the same, which is capable of accessing data in a continuous burst mode regardless of locations of accessed data. The semiconductor memory device includes: a first bank including a first word line corresponding to a first row address; and a second bank including a second word line corresponding to a second row address, wherein the second row address is consecutive to the first row address. The method for driving a semiconductor memory device includes the steps of: receiving a first row address corresponding to a command; activating a word line of a first bank corresponding to the first row address; activating a word line of a second bank corresponding to a second row address, in which the second row address is consecutive to the first row address; sequentially accessing the predetermined number of data among the N data in a plurality of unit cells corresponding to the word line of the first bank; and sequentially accessing the remaining data in a plurality of unit cells corresponding to a word line of the second bank.
摘要翻译：提供了一种半导体存储器件及其驱动方法，其能够以连续的突发模式访问数据，而不管访问数据的位置如何。半导体存储器件包括：第一存储体，包括对应于第一行地址的第一字线; 以及包括对应于第二行地址的第二字线的第二存储体，其中所述第二行地址与所述第一行地址连续。驱动半导体存储器件的方法包括以下步骤：接收与命令对应的第一行地址; 激活对应于第一行地址的第一存储体的字线; 激活对应于第二行地址的第二存储体的字线，其中第二行地址与第一行地址连续; 在对应于第一存储单元的字线的多个单位单元中，依次访问N个数据中的预定数量的数据; 并且依次访问与第二存储体的字线对应的多个单位单元中的剩余数据。

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