专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07051178B2 Burst write in a non-volatile memory device 有权
标题翻译：突发写入非易失性存储设备
公开(公告)号：US07051178B2
公开(公告)日：2006-05-23
申请号：US10747416
申请日：2003-12-29
申请人： Frankie F. Roohparvar
发明人： Frankie F. Roohparvar
IPC分类号： G06F12/00
CPC分类号： G11C7/1027 , G11C7/1018 , G11C7/1072 , G11C16/10 , G11C16/22 , G11C16/26 , G11C16/32
摘要： A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of rows and columns. During a read operation, a row of the memory array can be accessed and data written to a group of columns during a burst write operation. The burst columns are generated using an internal counter and an externally provided start address. Repeating sequences of commands and data packets are provided to the memory device. An externally provided data mask signal is used to write one of the data packets to the memory on each of the sequences.
摘要翻译：已经描述了包括非易失性存储器单元阵列的同步闪存。存储器件具有与SDRAM兼容的封装配置。同步闪速存储器件包括排列成多个行和列的非易失性存储单元阵列。在读取操作期间，可以访问存储器阵列的一行并且在突发写入操作期间将数据写入一组列。脉冲串列使用内部计数器和外部提供的起始地址生成。命令和数据包的重复序列被提供给存储器件。外部提供的数据掩码信号用于将每个数据包中的一个数据包写入每个序列上的存储器。

62. 发明授权

US07038966B2 Memory device and method having data path with multiple prefetch I/O configurations 失效
公开(公告)号：US07038966B2
公开(公告)日：2006-05-02
申请号：US11030844
申请日：2005-01-07
申请人： Brent Keeth , Brian Johnson , Troy A. Manning
发明人： Brent Keeth , Brian Johnson , Troy A. Manning
IPC分类号： G11C7/00
CPC分类号： G11C7/1072 , G11C7/1006 , G11C7/1018 , G11C7/1027 , G11C7/1045 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

63. 发明申请

US20060082478A1 Memory device and method having data path with multiple prefetch I/O configurations 有权
公开(公告)号：US20060082478A1
公开(公告)日：2006-04-20
申请号：US11284498
申请日：2005-11-21
申请人： Brent Keeth , Brian Johnson , Troy Manning
发明人： Brent Keeth , Brian Johnson , Troy Manning
IPC分类号： H03M9/00
CPC分类号： G11C7/1072 , G11C7/1006 , G11C7/1018 , G11C7/1027 , G11C7/1045 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

64. 发明授权

US06992944B2 Semiconductor memory device with reduced power consumption for refresh operation 失效
标题翻译：半导体存储器件具有降低功耗的刷新操作
公开(公告)号：US06992944B2
公开(公告)日：2006-01-31
申请号：US11079427
申请日：2005-03-15
申请人： Masato Takita , Kuninori Kawabata
发明人： Masato Takita , Kuninori Kawabata
IPC分类号： G11C7/00
CPC分类号： G11C7/1018 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4087
摘要： A semiconductor memory device includes a plurality of word decoders arranged in a plurality of columns, a plurality of word line selecting shift registers corresponding to the respective word decoders to indicate a word line subjected to refresh operation, and a shift control signal generating circuit operable to supply a shift control signal indicative of timing of shift operations to the plurality of word line selecting shift registers, wherein the said shift control signal generating circuit is configured to supply the shift control signal only to a column currently subjected to refresh operation among the plurality of columns.
摘要翻译：一种半导体存储器件，包括多列布置的多个字解码器，多个字线选择移位寄存器，其对应于各个字解码器，以指示经受刷新操作的字线;以及移位控制信号发生电路，向多个字线选择移位寄存器提供表示移位操作定时的移位控制信号，其中所述移位控制信号发生电路被配置为仅将移位控制信号提供给多个字线选择移位寄存器中当前经历刷新操作的列列。

65. 发明授权

US06992943B2 System and method for performing partial array self-refresh operation in a semiconductor memory device 有权
公开(公告)号：US06992943B2
公开(公告)日：2006-01-31
申请号：US10959804
申请日：2004-10-06
申请人： Hyong-Ryol Hwang , Jong-Hyun Choi , Hyun-Soon Jang
发明人： Hyong-Ryol Hwang , Jong-Hyun Choi , Hyun-Soon Jang
IPC分类号： G11C7/00
CPC分类号： G11C11/40622 , G11C7/1018 , G11C11/406 , G11C11/4087
摘要： Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or 1/16) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

66. 发明申请

US20050275470A1 Low power and low timing jitter phase-lock loop and method 失效
标题翻译：低功耗和低定时抖动锁相环和方法
公开(公告)号：US20050275470A1
公开(公告)日：2005-12-15
申请号：US10868284
申请日：2004-06-14
申请人： Dong Choi
发明人： Dong Choi
IPC分类号： G06F1/04 , H03L7/00 , H03L7/099
CPC分类号： G06F1/04 , G11C7/02 , G11C7/1006 , G11C7/1018 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/406 , G11C11/4076 , G11C11/4093 , H03L7/0891 , H03L7/0995 , H03L7/16 , H03L2207/10
摘要： A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.
摘要翻译：锁相环从输入时钟信号产生输出时钟信号。输出时钟信号通过时钟树耦合并被反馈到相位检测器，该相位检测器将输出时钟信号的相位与输入时钟信号的相位进行比较。输出时钟信号由具有耦合以接收来自相位检测器的输出的控制输入的压控振荡器和耦合到压控振荡器的输出的倍频器产生。结果，由倍频器产生的CLKOUT信号具有相对高的频率，而压控振荡器通过以较低的频率运行使用相对较小的功率。

67. 发明授权

US06930951B2 Semiconductor memory device capable of accessing data in continuous burst mode regardless of location of accessed data 有权
标题翻译：能够以连续脉冲串模式访问数据而不管访问数据的位置如何的半导体存储器件
公开(公告)号：US06930951B2
公开(公告)日：2005-08-16
申请号：US10744322
申请日：2003-12-22
申请人： Jin-Hong Ahn , Sang-Hoon Hong , Jae-Bum Ko , Se-Jun Kim
发明人： Jin-Hong Ahn , Sang-Hoon Hong , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G11C8/08 , G11C7/10 , G11C8/00 , G11C8/12
CPC分类号： G11C7/1018
摘要： There is provided a semiconductor memory device and a method for driving the same, which is capable of accessing data in a continuous burst mode regardless of locations of accessed data. The semiconductor memory device includes: a first bank including a first word line corresponding to a first row address; and a second bank including a second word line corresponding to a second row address, wherein the second row address is consecutive to the first row address. The method for driving a semiconductor memory device includes the steps of: receiving a first row address corresponding to a command; activating a word line of a first bank corresponding to the first row address; activating a word line of a second bank corresponding to a second row address, in which the second row address is consecutive to the first row address; sequentially accessing the predetermined number of data among the N data in a plurality of unit cells corresponding to the word line of the first bank; and sequentially accessing the remaining data in a plurality of unit cells corresponding to a word line of the second bank.
摘要翻译：提供了一种半导体存储器件及其驱动方法，其能够以连续的突发模式访问数据，而不管访问数据的位置如何。半导体存储器件包括：第一存储体，包括对应于第一行地址的第一字线; 以及包括对应于第二行地址的第二字线的第二存储体，其中所述第二行地址与所述第一行地址连续。驱动半导体存储器件的方法包括以下步骤：接收与命令对应的第一行地址; 激活对应于第一行地址的第一存储体的字线; 激活对应于第二行地址的第二存储体的字线，其中第二行地址与第一行地址连续; 在对应于第一存储单元的字线的多个单位单元中，依次访问N个数据中的预定数量的数据; 并且依次访问与第二存储体的字线对应的多个单位单元中的剩余数据。

68. 发明申请

US20050141328A1 Semiconductor memory device and method of reading data from semiconductor memory device 有权
标题翻译：半导体存储器件和从半导体存储器件读取数据的方法
公开(公告)号：US20050141328A1
公开(公告)日：2005-06-30
申请号：US11066484
申请日：2005-02-28
申请人： Kenji Nagai , Satoru Kawamoto
发明人： Kenji Nagai , Satoru Kawamoto
IPC分类号： G11C7/10 , G11C8/00 , G11C8/12 , G11C11/413
CPC分类号： G11C7/1018 , G11C7/103 , G11C8/12 , G11C11/413 , G11C2207/2245
摘要： A semiconductor memory device is arranged so that its circuit area is made smaller and the stored data may be constantly outputted at fast speed. The semiconductor memory device includes a memory cell array and an auxiliary cell array concatenated with word lines on the increasing side of bit-line addresses in the memory cell array. The auxiliary cell array stores data of memory cells in the range from a first bit-line address on a next word-line address to a bit-line address located apart by a predetermined number of bits. A Y-address driver is also included in the semiconductor memory device. The Y-address driver reads data from the auxiliary cell array following the last bit-line address if the read of data pieces at a time ranges from the last bit-line address to the first bit-line address on the next word-line address in the memory cell array.
摘要翻译：半导体存储器件被布置成使其电路面积更小，并且可以以快速的速度恒定地输出存储的数据。半导体存储器件包括存储单元阵列和与存储单元阵列中的位线地址的增加侧的字线连接的辅助单元阵列。辅助单元阵列将存储单元的数据存储在从下一个字线地址上的第一位线地址到分隔预定位数的位线地址的范围内。 Y地址驱动器也包括在半导体存储器件中。 Y地址驱动器从最后一个位线地址之后的辅助单元阵列读取数据，如果数据段的读取时间范围从下一个字线地址上的最后位线地址到第一个位线地址在存储单元阵列中。

69. 发明申请

US20050086595A1 Page boundary detector 失效
标题翻译：页边界检测器
公开(公告)号：US20050086595A1
公开(公告)日：2005-04-21
申请号：US10687991
申请日：2003-10-17
申请人： Kevin Campbell , Timothy Thompson , Christopher Paulson
发明人： Kevin Campbell , Timothy Thompson , Christopher Paulson
IPC分类号： G06F15/00 , G11C7/10 , G11C8/00
CPC分类号： G11C8/00 , G11C7/1018
摘要： A logical gate and a comparator are used to detect page boundaries in a data stream. A current address and a predetermined page size, that is an integer power of 2, are compared using a Boolean logic gate such as AND or XOR to detect a page boundary in a data stream. The output from the Boolean logic gate is compared to a predetermined value to cause a signal to be generated, indicating the end of the page.
摘要翻译：逻辑门和比较器用于检测数据流中的页边界。使用诸如AND或XOR之类的布尔逻辑门来比较当前地址和预定的页大小，即2的整数幂，以检测数据流中的页边界。将来自布尔逻辑门的输出与预定值进行比较，以产生指示页面结束的信号。

70. 发明授权

US06877064B2 Triggering of IO equilibrating ending signal with firing of column access signal 有权
标题翻译：触发IO平衡结束信号，同时触发列访问信号
公开(公告)号：US06877064B2
公开(公告)日：2005-04-05
申请号：US10284905
申请日：2002-10-31
申请人： Brendan N. Protzman , Timothy B. Cowles
发明人： Brendan N. Protzman , Timothy B. Cowles
IPC分类号： G11C7/10 , G11C7/22 , G11C11/409 , G06F12/00
CPC分类号： G11C11/409 , G11C7/1018 , G11C7/1072 , G11C7/22
摘要： A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.
摘要翻译：一种用于通过在读脉冲串期间允许IO线的上拉结束而在行地址锁存和列地址锁存（tRCD）之间改变时间的方法和装置，而不是等待下一个时钟信号的READ操作。在活动命令期间设置锁存器，以便设置节点电压，其允许IO上拉信号在列访问信号的触发时结束。本发明允许改进tRCD参数，并且允许数字线对在读取数据突发的第一位之前与IO线分离而不需要线共享。结果是在READ序列期间更精确和无错误地读取第一位数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式