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1. 发明授权

US08642422B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08642422B2
公开(公告)日：2014-02-04
申请号：US13315060
申请日：2011-12-08
申请人： Koji Shimbayashi
发明人： Koji Shimbayashi
IPC分类号： H01L21/8242
CPC分类号： H01L27/0811 , H01L27/088
摘要： In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate, layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.
摘要翻译：在构成从P型基板的表面添加有杂质的MOS晶体管的半导体器件中，栅极以下的区域即为不添加杂质的P型基板，第一和第二MOS 具有N型扩散层的器件设置在与栅极层对置的P型基板的表面区域上。连接第一MOS器件的栅极层和第二MOS器件的N型扩散层，并且连接第一MOS器件的N型扩散层和第二MOS器件的栅极层，从而组成第一电容元件。

2. 发明授权

US06917541B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06917541B2
公开(公告)日：2005-07-12
申请号：US10060185
申请日：2002-02-01
申请人： Koji Shimbayashi , Takaaki Furuyama
发明人： Koji Shimbayashi , Takaaki Furuyama
IPC分类号： G11C16/06 , G11C7/18 , G11C16/04 , G11C16/24 , G11C16/28
CPC分类号： G11C16/24 , G11C7/18 , G11C16/28
摘要： This invention provides a nonvolatile semiconductor memory device including a novel memory core portion in which an influence of a parasitic element component in a memory cell information reading path is excluded in a reading operation, and novel sensing means accompanying this memory core structure, so as to achieve rapid sensing. In the memory core portion, a selected memory cell is selected by a global bit line through a local bit line and an adjacent global bit line is connected to a local bit line in a non-selected sector. A column selecting portion connects a pair of the global bit lines to a pair of data bus lines. A load portion having a load equivalent to a parasitic capacitance of a path leading from the memory cell and for supplying a reference current to a reference side is connected to a pair of the data bus lines. A current of the memory cell information is compared with the reference current by a current comparing portion and a differential current is outputted. A path load is equalized by a pair of adjacent paths so that an effect from noise is canceled, thus making it possible to achieve rapid reading.
摘要翻译：本发明提供了一种非易失性半导体存储器件，其包括新颖的存储器芯部分，其中在读取操作中排除了存储器单元信息读取路径中的寄生元件分量的影响，以及伴随该存储器核心结构的新型感测装置，实现快速感知。在存储器核心部分中，通过局部位线的全局位线选择选定的存储单元，并且相邻的全局位线连接到非选择扇区中的本地位线。列选择部分将一对全局位线连接到一对数据总线。具有与从存储单元引出的路径的寄生电容相当并且用于向参考侧提供参考电流的负载的负载部分连接到一对数据总线。通过电流比较部分将存储单元信息的电流与参考电流进行比较，并输出差分电流。路径负载由一对相邻的路径相等，从而消除噪声的影响，从而可以实现快速读取。

3. 发明授权

US07940570B2 Memory employing separate dynamic reference areas 有权
标题翻译：内存采用单独的动态参考区域
公开(公告)号：US07940570B2
公开(公告)日：2011-05-10
申请号：US12494104
申请日：2009-06-29
申请人： Kenta Kato , Masahiro Niimi , Koji Shimbayashi
发明人： Kenta Kato , Masahiro Niimi , Koji Shimbayashi
IPC分类号： G11C16/04 , G11C7/02
CPC分类号： G11C7/14 , G11C16/28
摘要： A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal.
摘要翻译：使用单独的动态参考（Dref）区域来提供阈值电压参考信号的存储器。存储器包括单独的Dref区域，位于Dref区域之间的数据区域，参考阵列和一个或多个读出放大器。数据区被配置为提供输出信号，参考单元和单独的D ref区域被布置成提供阈值电压参考信号，并且读出放大器布置成接收输出信号和阈值电压参考信号。

4. 发明授权

US07239576B2 Memory device and method of controlling the same 有权
标题翻译：存储器件及其控制方法
公开(公告)号：US07239576B2
公开(公告)日：2007-07-03
申请号：US11342013
申请日：2006-01-27
申请人： Koji Shimbayashi
发明人： Koji Shimbayashi
IPC分类号： G11C8/18
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1063 , G11C7/1066
摘要： In a single data rate (SDR) mode, logic level transitions of a data condition prior-determination signal RDYO are outputted to an output terminal (O) in response to an internal clock signal CKI. A ready signal RDY is outputted in synchronization with the internal clock signal CKI following a logic level transition of the data condition prior-determination signal RDYO. In a double data rate (DDR) mode, on the other hand, a toggle signal is outputted to the output terminal (O) in correspondence with the internal clock signal CKI following a logical level transition of the data condition prior-determination signal RDYO. After the internal clock signal CKI following the logical level transition of the data condition prior-determination signal RDYO, a strobe signal DQS is outputted in synchronization with the internal clock signal CKI. The ready signal RDY is outputted at the data condition informing terminal (X) in SDR mode while, on the other hand, the strobe signal DQS is outputted at the data condition informing terminal (X) in DDR mode.
摘要翻译：在单个数据速率（SDR）模式中，响应于内部时钟信号CKI，将数据条件先前确定信号RDYO的逻辑电平转换输出到输出端（O）。在数据条件先决判定信号RDYO的逻辑电平转换之后，与内部时钟信号CKI同步输出就绪信号RDY。另一方面，在双倍数据速率（DDR）模式中，与数据条件先前确定信号RDYO的逻辑电平转换之后的内部时钟信号CKI对应地，向输出端子（O）输出触发信号。在数据条件判定信号RDYO的逻辑电平转换之后的内部时钟信号CKI之后，与内部时钟信号CKI同步地输出选通信号DQS。准备信号RDY以SDR模式在数据条件通知终端（X）输出，另一方面，在数据条件通知终端（X）以DDR模式输出选通信号DQS。

5. 发明申请

US20120080735A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120080735A1
公开(公告)日：2012-04-05
申请号：US13314932
申请日：2011-12-08
申请人： Koji SHIMBAYASHI
发明人： Koji SHIMBAYASHI
IPC分类号： H01L27/108
CPC分类号： H01L27/0811 , H01L27/088
摘要： In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.
摘要翻译：在构成从P型基板的表面添加有杂质的MOS晶体管的半导体装置中，栅极层以下的区域是不添加杂质的P型基板，第一和第二MOS元件在具有栅极层的P型基板的表面区域上设置有N型扩散层。连接第一MOS器件的栅极层和第二MOS器件的N型扩散层，并且连接第一MOS器件的N型扩散层和第二MOS器件的栅极层，从而组成第一电容元件。

6. 发明授权

US08076753B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08076753B2
公开(公告)日：2011-12-13
申请号：US11479373
申请日：2006-06-30
申请人： Koji Shimbayashi
发明人： Koji Shimbayashi
IPC分类号： H01L29/00
CPC分类号： H01L27/0811 , H01L27/088
摘要： In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.
摘要翻译：在构成从P型基板的表面添加有杂质的MOS晶体管的半导体装置中，栅极层以下的区域是不添加杂质的P型基板，第一和第二MOS元件在具有栅极层的P型基板的表面区域上设置有N型扩散层。连接第一MOS器件的栅极层和第二MOS器件的N型扩散层，并且连接第一MOS器件的N型扩散层和第二MOS器件的栅极层，从而组成第一电容元件。

7. 发明申请

US20060227629A1 Memory device and control method therefor 有权
标题翻译：存储器及其控制方法
公开(公告)号：US20060227629A1
公开(公告)日：2006-10-12
申请号：US11378444
申请日：2006-03-16
申请人： Koji Shimbayashi , Takaaki Furuyama , Kenji Shibata
发明人： Koji Shimbayashi , Takaaki Furuyama , Kenji Shibata
IPC分类号： G11C7/06
CPC分类号： G11C7/08 , G11C7/1018 , G11C16/26 , G11C16/32
摘要： An access identification circuit (4) identifies a first access operation or a second access operation and outputs an identification signal S. During the first access operation, stored data is read out after detecting a column address CADD, a burst address, and updating a word line to newly select memory cells MC. In the second access operation, the memory cells MC connected to the common word line which has been selected are selected by sequentially switching column selector switches. Operating condition information Dx (DAx and/or DBx) used for setting a load condition in a dummy load circuit (5) and/or setting a pulse width for an equalize signal EQ in an amplification control circuit (6) is stored in each of first and second storage sections (1, 2) that are provided for the first and second access operations, respectively. The operating condition information Dx is selected by a selector circuit (3) in response to the identification signal S and fed to the dummy load circuit (5) and/or the amplification control circuit (6). A suitable operating condition is selected for each of the access operations.
摘要翻译：访问识别电路（4）识别第一访问操作或第二访问操作并输出识别信号S.在第一访问操作期间，在检测列地址CADD，突发地址和更新字之后读出存储的数据行新选择存储单元MC。在第二访问操作中，通过依次切换列选择器开关来选择连接到所选择的公共字线的存储单元MC。在放大控制电路（6）中用于设置虚拟负载电路（5）中的负载条件和/或设定均衡信号EQ的脉冲宽度的工作条件信息Dx（DAx和/或DBx）被存储在分别为第一和第二存取操作提供的第一和第二存储部分（1,2）。操作条件信息Dx由选择器电路（3）响应于识别信号S选择并馈送到虚拟负载电路（5）和/或放大控制电路（6）。为每个访问操作选择合适的操作条件。

8. 发明授权

US08698280B2 Capacitive element using MOS transistors 有权
标题翻译：使用MOS晶体管的电容元件
公开(公告)号：US08698280B2
公开(公告)日：2014-04-15
申请号：US13314932
申请日：2011-12-08
申请人： Koji Shimbayashi
发明人： Koji Shimbayashi
IPC分类号： H01L29/00
CPC分类号： H01L27/0811 , H01L27/088
摘要： In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.
摘要翻译：在构成从P型基板的表面添加有杂质的MOS晶体管的半导体装置中，栅极层以下的区域是不添加杂质的P型基板，第一和第二MOS元件在具有栅极层的P型基板的表面区域上设置有N型扩散层。连接第一MOS器件的栅极层和第二MOS器件的N型扩散层，并且连接第一MOS器件的N型扩散层和第二MOS器件的栅极层，从而组成第一电容元件。

9. 发明申请

US20100329003A1 MEMORY EMPLOYING INDEPENDENT DYNAMIC REFERENCE AREAS 有权
标题翻译：使用独立动态参考区域的记忆
公开(公告)号：US20100329003A1
公开(公告)日：2010-12-30
申请号：US12494114
申请日：2009-06-29
申请人： Kenta Kato , Masahiro Niimi , Koji Shimbayashi
发明人： Kenta Kato , Masahiro Niimi , Koji Shimbayashi
IPC分类号： G11C16/06 , G11C7/02
CPC分类号： G11C16/28 , G11C7/14
摘要： A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line.
摘要翻译：采用独立访问的独立Dref区域以提供阈值电压参考信号的存储器。存储器包括单独的Dref区域，位于Dref区域之间的数据区域，一个或多个读出放大器和开关组件。开关部件布置成接收寻址数据，并且至少部分地基于单个存储器单元沿着字线的物理接近度将独立的Dref区域独立地耦合到读出放大器。

10. 发明授权

US07605616B2 Voltage detector circuit 有权
标题翻译：电压检测电路
公开(公告)号：US07605616B2
公开(公告)日：2009-10-20
申请号：US11975097
申请日：2007-10-16
申请人： Koji Shimbayashi
发明人： Koji Shimbayashi
IPC分类号： H03K5/153
CPC分类号： G01R19/16557 , G01R19/16571 , G11C5/143 , G11C5/147
摘要： A voltage detection circuit for accurately detecting a voltage that is unaffected by fluctuation due to variations in transistor characteristics and threshold voltage. The voltage detection circuit includes a reference current generating section and a detecting section. The reference current generating section includes a voltage-controlled current source that includes a control terminal, a reference terminal and an output terminal. The reference current generating section generates an output current that serves as a reference current and output to a current mirroring circuit. The detecting section includes a number of voltage-controlled current sources each with the same configuration as the voltage-controlled current sources in the current generating section. A potential to be detected is input into the detecting section. A target potential is calculated as the set potential multiplied by the number of voltage-controlled current sources in the detecting section. When the absolute value of the potential to be detected equals the target potential, the currents in each of the voltage-controlled current sources in the detecting section is set equal to the set potential. Due to the equivalent configurations of the voltage-controlled current sources, the current flowing in the reference current generating section is balanced with, and becomes equal to the current in the detecting section. The detection is made by current comparison between the reference current output from the reference current generating section and the detection current flowing in the detecting section.
摘要翻译：一种电压检测电路，用于精确地检测由于晶体管特性和阈值电压的变化而不受波动影响的电压。电压检测电路包括基准电流产生部分和检测部分。基准电流产生部分包括一个包括控制端子，参考端子和输出端子的压控电流源。参考电流产生部分产生用作参考电流并输出到电流镜像电路的输出电流。检测部分包括多个电压控制电流源，每个具有与电流产生部分中的电压控制电流源相同的配置。将被检测的电位输入到检测部。计算目标电位作为设定电位乘以检测部中的电压控制电流源的数量。当待检测电位的绝对值等于目标电位时，检测部分中每个电压控制电流源中的电流设定为等于设定电位。由于电压控制电流源的等效结构，在参考电流产生部分中流动的电流与检测部分中的电流平衡并变成等于电流。通过从参考电流产生部分输出的参考电流与在检测部分中流动的检测电流之间的电流比较来进行检测。

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