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61. 发明申请

US20130134511A1 Semiconductor Device with Self-Biased Isolation 有权
标题翻译：具有自偏置隔离的半导体器件
公开(公告)号：US20130134511A1
公开(公告)日：2013-05-30
申请号：US13307449
申请日：2011-11-30
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L21/761
CPC分类号： H01L29/063 , H01L21/761 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/423 , H01L29/66659 , H01L29/7835
摘要： A device includes a semiconductor substrate including a surface, a drain region in the semiconductor substrate having a first conductivity type, a well region in the semiconductor substrate on which the drain region is disposed, the well region having the first conductivity type, a buried isolation layer in the semiconductor substrate extending across the well region, the buried isolation layer having the first conductivity type, a reduced surface field (RESURF) region disposed between the well region and the buried isolation layer, the RESURF region having a second conductivity type, and a plug region in the semiconductor substrate extending from the surface of the substrate to the RESURF region, the plug region having the second conductivity type.
摘要翻译：一种器件包括：具有表面的半导体衬底，具有第一导电类型的半导体衬底中的漏极区，设置有漏极区的半导体衬底中的阱区，具有第一导电类型的阱区，所述半导体衬底中延伸穿过所述阱区，所述掩埋隔离层具有第一导电类型，设置在所述阱区和所述掩埋隔离层之间的还原表面场（RESURF）区，所述RESURF区具有第二导电类型，以及所述半导体衬底中的插塞区域从所述衬底的表面延伸到所述RESURF区域，所述插塞区域具有所述第二导电类型。

62. 发明申请

US20120043608A1 Partially Depleted Dielectric Resurf LDMOS 有权
标题翻译：部分耗尽的电介质解决方案LDMOS
公开(公告)号：US20120043608A1
公开(公告)日：2012-02-23
申请号：US12860565
申请日：2010-08-20
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0873 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/1083 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： An partially depleted Dieler LDMOSFET transistor (100) is provided which includes a substrate (150), a drift region (110) surrounding a drain region (128), a first well region (107) surrounding source region (127), a well buffer region (106) separating the drift region and first well region to at least partly define a first channel region, a gate electrode (118) formed over the first channel region having a source-side gate edge aligned with the first well region (107), an LDD extension region (120) extending from the source region to the channel region, and a dielectric RESURF drain extension structure (161) formed at the drain of the gate electrode (118) using the plurality of STI stripes (114).
摘要翻译：提供了部分耗尽的Dieler LDMOSFET晶体管（100），其包括衬底（150），围绕漏极区域（128）的漂移区域（110），围绕源区域（127）的第一阱区域（107）分离漂移区域和第一阱区域以至少部分地限定第一沟道区域的区域（106），形成在具有与第一阱区域（107）对准的源极侧边沿的第一沟道区域上的栅电极（118），从源极区域延伸到沟道区域的LDD延伸区域（120）以及使用多个STI条纹（114）形成在栅电极（118）的漏极处的介电RESURF漏极延伸结构（161）。

63. 发明授权

US07927955B2 Adjustable bipolar transistors formed using a CMOS process 有权
标题翻译：使用CMOS工艺形成的可调双极晶体管
公开(公告)号：US07927955B2
公开(公告)日：2011-04-19
申请号：US12142115
申请日：2008-06-19
申请人： Xin Lin , Bernhard H. Grote , Hongning Yang , Jiang-Kai Zuo
发明人： Xin Lin , Bernhard H. Grote , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L21/331
CPC分类号： H01L29/7322 , H01L21/8222 , H01L21/8249 , H01L29/0821 , H01L29/1004 , H01L29/66272
摘要： By providing a novel bipolar device design implementation, a standard CMOS process (105-109) can be used unchanged to fabricate useful bipolar transistors (80) and other bipolar devices having adjustable properties by partially blocking the P or N well doping (25) used for the transistor base (581). This provides a hump-shaped base (583, 584) region with an adjustable base width (79), thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process (101-104) alone. By further partially blocking the source/drain doping step (107) used to form the emitter (74) of the bipolar transistor (80), the emitter shape and effective base width (79) can be further varied to provide additional control over the bipolar device (80) properties. The embodiments thus include prescribed modifications to the masks (57, 62, 72, 46) associated with the bipolar device (80) that are configured to obtain desired device properties. The CMOS process steps (105-109) and flow are otherwise unaltered and no additional process steps are required.
摘要翻译：通过提供一种新颖的双极器件设计实现，标准CMOS工艺（105-109）可以不变地用于制造有用的双极晶体管（80）和其他具有可调整特性的双极器件，通过部分阻塞使用的P或N阱掺杂（25）用于晶体管基极（581）。这提供了具有可调底座宽度（79）的驼峰形基部（583,584）区域，从而实现例如比仅用未修改的CMOS工艺（101-104）可获得的增益更高的增益。通过进一步部分地阻挡用于形成双极晶体管（80）的发射极（74）的源/漏掺杂步骤（107），可以进一步改变发射极形状和有效基极宽度（79），以提供对双极晶体管设备（80）属性。因此，这些实施例包括与被配置为获得期望的器件特性的与双极器件（80）相关联的掩模（57,62,72,46）的规定修改。 CMOS工艺步骤（105-109）和流程否则不变，并且不需要额外的工艺步骤。

64. 发明授权

US07910991B2 Dual gate lateral diffused MOS transistor 有权
标题翻译：双栅极横向扩散MOS晶体管
公开(公告)号：US07910991B2
公开(公告)日：2011-03-22
申请号：US12060105
申请日：2008-03-31
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/76
CPC分类号： H01L27/0705 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/41775 , H01L29/66659 , H01L29/7831 , H01L29/7835
摘要： A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions.
摘要翻译：适用于可以以超过例如5MHz或更大的开关频率工作的开关模式转换器的公开的功率晶体管包括覆盖在半导体衬底的上表面上的栅极电介质层和覆盖的半导体衬底的第一和第二栅电极栅介质层。第一栅电极横向定位成覆盖在衬底的第一区域上。第一衬底区域具有第一类型的掺杂，其可以是n型或p型。功率晶体管的第二栅电极覆盖栅极电介质，并且横向地位于衬底的第二区域上方。第二衬底区域具有与第一类型不同的第二掺杂类型。晶体管还包括位于衬底内的漂移区域，该漂移区域紧邻衬底的上表面并横向地位于第一和第二衬底区域之间。

65. 发明授权

US07910441B2 Multi-gate semiconductor device and method for forming the same 有权
标题翻译：多栅半导体器件及其形成方法
公开(公告)号：US07910441B2
公开(公告)日：2011-03-22
申请号：US11489793
申请日：2006-07-19
申请人： Hongning Yang , Xin Lin , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Jiang-Kai Zuo
IPC分类号： H01L21/8234
CPC分类号： H01L29/66484 , H01L29/1041 , H01L29/7831 , H01L29/7833
摘要： A semiconductor device includes a substrate (20), a source region (58) formed over the substrate, a drain region (62) formed over the substrate, a first gate electrode (36) over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode (38) over the substrate adjacent to the drain region and between the source and drain regions.
摘要翻译：半导体器件包括衬底（20），形成在衬底上的源区（58），形成在衬底上的漏区（62），与源区相邻的衬底上的第一栅极（36）源极和漏极区域以及与漏极区域相邻并且在源极和漏极区域之间的衬底上的第二栅电极（38）。

66. 发明授权

US07700417B2 Methods for forming cascode current mirrors 有权
标题翻译：形成共源共栅电流镜的方法
公开(公告)号：US07700417B2
公开(公告)日：2010-04-20
申请号：US11686439
申请日：2007-03-15
申请人： Hongning Yang , Geoffrey W. Perkins , Jiang-Kai Zuo
发明人： Hongning Yang , Geoffrey W. Perkins , Jiang-Kai Zuo
IPC分类号： H01L21/00
CPC分类号： H01L29/7833 , H01L21/823425 , H01L21/823456 , H01L21/823462 , H01L27/088 , H01L29/6659 , Y10S438/981
摘要： A cascode amplifier (CA) (60) is described having a bottom transistor (T1new) with a relatively thin gate dielectric (67) and higher ratio (RB) of channel length (Lch1new) to width (W1new) and a series coupled top transistor (T2new) with a relatively thick gate dielectric (68) and a lower ratio (RT) of channel length (Lch2new) to width (W2new). An improved cascode current mirror (CCM) (74) is formed using a coupled pair of CAs (60, 60′), one (60) forming the reference current (RC) side (601) and the other (60′) forming the mirror current side (602) of the CCM (74). The gates (65, 65′) of the bottom transistors (T1new, T3new) are tied together and to the common node (21) between the series coupled bottom (T1new) and top (T2new) transistors of the RC side (601), and the gates (66′, 66′) of the top transistors (T2new, T4new) are coupled together and to the top drain node (64) of the RC side (601). The area of the CCM (74) can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.
摘要翻译：描述了一种级联放大器（CA）（60），其具有具有相对薄的栅极电介质（67）和沟道长度（Lch1new）至宽度（W1new）的更高比率（RB））的底部晶体管（T1new）和串联耦合顶部晶体管（T2new），具有相对较厚的栅极电介质（68）和沟道长度（Lch2new）与宽度（W2new）的较低比率（RT）。使用耦合的一对CA（60,60'），形成基准电流（RC）侧（601）的一个（60）和形成基准电流（RC））的另一个（60'）形成改进的共源共栅电流镜（CC） CCM（74）的镜电流侧（602）。底部晶体管（T1new，T3new）的栅极（65,65'）被连接到RC侧（601）的串联耦合的底部（T1new）和顶部（T2new）晶体管之间的公共节点（21）并且顶部晶体管（T2new，T4new）的栅极（66'，66'）耦合在一起并连接到RC侧（601）的顶部漏极节点（64）。 CCM（74）的面积可以基本上缩小，而不会对匹配，噪声性能和最大允许工作电压产生不利影响。

67. 发明申请

US20080224237A1 SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件
公开(公告)号：US20080224237A1
公开(公告)日：2008-09-18
申请号：US12129861
申请日：2008-05-30
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L21/26586 , H01L21/823807 , H01L21/823892 , H01L29/1045 , H01L29/1083 , H01L29/66659
摘要： An embodiment of a semiconductor device includes a gate electrode overlying a substrate and a lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms a gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain.
摘要翻译：半导体器件的实施例包括覆盖衬底的栅电极和形成在衬底上的轻掺杂外延层。高能注入区域在轻掺杂外延层的源极侧形成阱。自对准的晕圈植入区域形成在器件的源极侧和高能阱植入体内。在轻掺杂外延层的漏极侧的注入区域形成栅极重叠LDD（GOLD）。卤素注入区域内的掺杂区域形成源。栅极重叠LDD（GOLD）内的掺杂区域形成漏极。

68. 发明申请

US20080121997A1 Multi-gate semiconductor device and method for forming the same 有权
标题翻译：多栅半导体器件及其形成方法
公开(公告)号：US20080121997A1
公开(公告)日：2008-05-29
申请号：US11489793
申请日：2006-07-19
申请人： Hongning Yang , Xin Lin , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L21/04
CPC分类号： H01L29/66484 , H01L29/1041 , H01L29/7831 , H01L29/7833
摘要： A semiconductor device includes a substrate (20), a source region (58) formed over the substrate, a drain region (62) formed over the substrate, a first gate electrode (36) over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode (38) over the substrate adjacent to the drain region and between the source and drain regions.
摘要翻译：半导体器件包括衬底（20），形成在衬底上的源区（58），形成在衬底上的漏区（62），与源区相邻的衬底上的第一栅极（36）源极和漏极区域以及与漏极区域相邻并且在源极和漏极区域之间的衬底上的第二栅电极（38）。

69. 发明申请

US20070020832A1 Semiconductor devices and method of fabrication 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070020832A1
公开(公告)日：2007-01-25
申请号：US11189587
申请日：2005-07-25
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7835 , H01L21/26586 , H01L21/823807 , H01L21/823892 , H01L29/1045 , H01L29/1083 , H01L29/66659
摘要： A semiconductor having an ˜5V operational range, including a drain side enhanced gate-overlapped LDD (GOLD) and a source side halo implant region and well implant. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and a very lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms the gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain. The structure enables the manufacture of a deep submicron (
摘要翻译：具有〜5V工作范围的半导体，包括漏极侧增强的栅极重叠LDD（GOLD）和源极晕圈注入区域以及阱注入。根据本发明的实施例的方法包括形成覆盖衬底的栅电极和形成在衬底上的非常轻掺杂的外延层。高能注入区域在轻掺杂外延层的源极侧形成阱。自对准的晕圈植入区域形成在器件的源极侧和高能阱植入体内。在轻掺杂外延层的漏极侧的注入区域形成栅极重叠的LDD（GOLD）。卤素注入区域内的掺杂区域形成源。栅极重叠LDD（GOLD）内的掺杂区域形成漏极。该结构使得能够使用现有的0.13mum工艺流程制造深亚微米（<0.3mum）的功率MOSFET，而无需额外的掩模和处理步骤。

70. 发明授权

US09401412B2 Methods of fabricating diodes with multiple junctions 有权
标题翻译：制造具有多个结的二极管的方法
公开(公告)号：US09401412B2
公开(公告)日：2016-07-26
申请号：US14804097
申请日：2015-07-20
申请人： Xin Lin , Hongning Yang , Jiang-Kai Zuo
发明人： Xin Lin , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L21/336 , H01L29/66 , H01L29/861 , H01L29/06 , H01L21/3205 , H01L21/265 , H01L29/08
CPC分类号： H01L29/66121 , H01L21/265 , H01L21/26513 , H01L21/32053 , H01L29/0649 , H01L29/08 , H01L29/6609 , H01L29/66128 , H01L29/861 , H01L29/8611
摘要： An embodiment of a method of fabricating a diode having a plurality of regions of a first conductivity type and a buried region of a second conductivity type includes performing a first dopant implantation procedure to form the buried region, performing a second dopant implantation procedure to form an intermediate region of the plurality of regions, and performing a third dopant implantation procedure to form a contact region of the plurality of regions. The second and third dopant implantation procedures are configured such that the intermediate region is electrically connected with the contact region. The first, second, and third dopant implantation procedures are configured such that the buried region extends laterally across the contact region and the intermediate region to establish first and second junctions of the diode, respectively, and such that the first junction has a lower breakdown voltage than the second junction.
摘要翻译：制造具有第一导电类型的多个区域和第二导电类型的掩埋区域的二极管的方法的实施例包括执行第一掺杂剂注入步骤以形成掩埋区域，执行第二掺杂剂注入工艺以形成并且执行第三掺杂剂注入过程以形成所述多个区域的接触区域。第二和第三掺杂剂注入程序被配置为使得中间区域与接触区域电连接。第一，第二和第三掺杂剂注入过程被配置为使得掩埋区域横向延伸穿过接触区域和中间区域以分别建立二极管的第一和第二结，并且使得第一结点具有较低的击穿电压比第二交界处。

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