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61. 发明授权

US06545904B2 6F2 DRAM ARRAY, A DRAM ARRAY FORMED ON A SEMICONDUCTIVE SUBSTRATE, A METHOD OF FORMING MEMORY CELLS IN A 6F2 DRAM ARRAY AND A METHOD OF ISOLATING A SINGLE ROW OF MEMORY CELLS IN A 6F2 DRAM ARRAY 有权
标题翻译： 6F2 DRAM阵列，在半导体衬底上形成的DRAM阵列，在6F2 DRAM阵列中形成存储器单元的方法和在6F2 DRAM阵列中分离存储器单元的单行方法
公开(公告)号：US06545904B2
公开(公告)日：2003-04-08
申请号：US09810933
申请日：2001-03-16
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： G11C700
CPC分类号： H01L27/10873 , H01L27/0214 , H01L27/10894 , Y10S257/906 , Y10S438/981
摘要： The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.
摘要翻译：本发明包括形成在半导体衬底上的6F2 DRAM阵列。存储器阵列包括第一存储单元。第一存储单元包括第一存取晶体管和第一数据存储电容器。第一存取晶体管的第一负载电极经由形成在衬底上的第一存储节点耦合到第一数据存储电容器。存储器阵列还包括第二存储器单元。第二存储单元包括第二存取晶体管和第二数据存储电容器。第二存取晶体管的第一负载电极经由形成在基板上的第二存储节点耦合到第二数据存储电容器。第一和第二存取晶体管具有具有第一厚度的栅极电介质。存储器阵列还包括形成在第一和第二存储节点之间并被配置为在它们之间提供电隔离的隔离栅极。隔离栅极具有第二厚度大于第一厚度的栅极电介质。隔离栅极电介质可以在衬底的表面上方或下方延伸。

62. 发明授权

US5943579A Method for forming a diffusion region in a semiconductor device 失效
标题翻译：在半导体器件中形成扩散区域的方法
公开(公告)号：US5943579A
公开(公告)日：1999-08-24
申请号：US799233
申请日：1997-02-14
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L21/8244 , H01L21/331
CPC分类号： H01L27/11
摘要： A semiconductor processing method for forming a diffusion region is described and which includes providing a semiconductor substrate; forming a first layer of material over the semiconductor substrate; and after forming the first layer, ion implanting a conductivity modifying impurity through the first layer and into the semiconductor substrate to form a diffusion region therein. In an alternative form, a method for forming a field effect transistor is described and which includes providing a substrate; forming a field oxide region and active area region on the substrate; forming a gate dielectric layer atop the substrate and within the active area region; and after forming the gate dielectric layer, ion implanting a dopant impurity through the field oxide region and into the underlying substrate to form a field implant beneath the field oxide region for facilitating electrical isolation of the field effect transistor from adjacent electrical devices. In a third form of the invention, a method for forming a background dopant well relative to a semiconductor substrate is described and which includes providing a semiconductor substrate; forming a field oxide region on the semiconductor substrate; forming a gate dielectric layer atop the semiconductor substrate; forming a conductive gate layer atop the gate dielectric layer; and after forming the conductive gate layer, ion implanting through the field oxide region, gate dielectric layer, and conductive gate layer to form a background dopant well.
摘要翻译：描述了用于形成扩散区域的半导体处理方法，其包括提供半导体衬底; 在半导体衬底上形成第一层材料; 并且在形成第一层之后，通过第一层离子注入导电性修饰杂质并进入半导体衬底以在其中形成扩散区。在替代形式中，描述了形成场效应晶体管的方法，其包括提供衬底; 在衬底上形成场氧化物区域和有源区域区域; 在衬底顶部和有源区域内形成栅介电层; 并且在形成栅极电介质层之后，离子通过场氧化物区域注入掺杂剂杂质并进入下面的衬底中以在场氧化物区域下形成场注入，以便于将场效应晶体管与相邻电器件电隔离。在本发明的第三种形式中，描述了相对于半导体衬底形成背景掺杂剂的方法，其包括提供半导体衬底; 在半导体衬底上形成场氧化物区域; 在所述半导体衬底的顶部形成栅介质层; 在所述栅极介电层的顶部形成导电栅极层; 并且在形成导电栅极层之后，通过场氧化物区域，栅极介电层和导电栅极层离子注入，以形成背景掺杂剂。

63. 发明授权

US08723326B2 Semiconductor structures including tight pitch contacts 有权
标题翻译：包括紧密节距触点的半导体结构
公开(公告)号：US08723326B2
公开(公告)日：2014-05-13
申请号：US13194558
申请日：2011-07-29
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L23/48
CPC分类号： H01L21/76802 , H01L21/02164 , H01L21/0228 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/3141 , H01L21/31608 , H01L21/7681 , H01L21/76816 , H01L21/76877 , H01L23/481 , H01L27/108 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.
摘要翻译：制造具有与有源区域特征对准的紧密节距触点的半导体结构的方法，并且使用用于限定具有亚光刻尺寸的图案的各种技术同时制造自对准的紧密节距触点和导线。还公开了具有与有源区域特征对准的紧密节距触点的半导体结构以及可选地对齐的导线，半导体结构具有紧密的节距接触孔和用于导线的对准的沟槽。

64. 发明授权

US08481417B2 Semiconductor structures including tight pitch contacts and methods to form same 有权
标题翻译：半导体结构包括紧密节距触点和形成相同的方法
公开(公告)号：US08481417B2
公开(公告)日：2013-07-09
申请号：US11833386
申请日：2007-08-03
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L21/44
CPC分类号： H01L21/76802 , H01L21/02164 , H01L21/0228 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/3141 , H01L21/31608 , H01L21/7681 , H01L21/76816 , H01L21/76877 , H01L23/481 , H01L27/108 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.
摘要翻译：制造具有与有源区域特征对准的紧密节距触点的半导体结构的方法，并且使用用于限定具有亚光刻尺寸的图案的各种技术同时制造自对准的紧密节距触点和导线。还公开了具有与有源区域特征对准的紧密节距触点的半导体结构以及可选地对齐的导线，半导体结构具有紧密的节距接触孔和用于导线的对准的沟槽。

65. 发明授权

US08158476B2 Integrated circuit fabrication 有权
标题翻译：集成电路制造
公开(公告)号：US08158476B2
公开(公告)日：2012-04-17
申请号：US12850511
申请日：2010-08-04
申请人： Luan C. Tran , John Lee , Zengtao “Tony” Liu , Eric Freeman , Russell Nielsen
发明人： Luan C. Tran , John Lee , Zengtao “Tony” Liu , Eric Freeman , Russell Nielsen
IPC分类号： H01L21/8242
CPC分类号： H01L21/0334 , H01L21/0337 , H01L21/0338 , H01L21/30604 , H01L21/3083 , H01L21/31144 , H01L21/76816 , H01L21/76877 , H01L21/76897 , H01L23/544 , H01L27/1052 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.
摘要翻译：用于限定集成电路中的图案的方法包括在衬底的第一区域上使用光刻法在第一光致抗蚀剂层中限定多个特征。该方法还包括使用音调倍增以在光致抗蚀剂层中的每个特征的下掩蔽层中产生至少两个特征。下掩蔽层中的特征包括环形端。该方法还包括用第二光致抗蚀剂层覆盖包括下掩蔽层中的环状末端的衬底的第二区域。该方法还包括通过下掩蔽层中的特征蚀刻衬底中的沟槽图案，而不在第二区域内进行蚀刻。沟槽具有沟槽宽度。

66. 发明申请

US20120025869A1 NON-VOLATILE FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：非挥发性可编程门阵列
公开(公告)号：US20120025869A1
公开(公告)日：2012-02-02
申请号：US13209704
申请日：2011-08-15
申请人： Chih-Wei Hung , Chia-Ta Hsieh , Luan C. Tran
发明人： Chih-Wei Hung , Chia-Ta Hsieh , Luan C. Tran
IPC分类号： H03K19/177
CPC分类号： G11C16/10 , G11C16/0441 , H03K19/1776
摘要： A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The first and second CMOS devices are complementary to one another. An output node is coupled between the first CMOS device and the second CMOS device. A method of programming a non-volatile field programmable gate array (NV-FPGA) includes coupling an information handling system to the FPGA, performing a block erase of a plurality of memory cells in the FPGA, verifying that the block erase is successful, programming an upper page of the FPGA, verifying that the upper page programming is successful, programming a lower page of the FPGA and verifying that the lower page programming is successful.
摘要翻译：非易失性存储器件包括耦合到位线和字线的第一金属氧化物半导体（CMOS）器件和耦合到第一CMOS器件的第二CMOS器件。第二CMOS器件还耦合到互补位线和互补字线。第一和第二CMOS器件彼此互补。输出节点耦合在第一CMOS器件和第二CMOS器件之间。编程非易失性现场可编程门阵列（NV-FPGA）的方法包括将信息处理系统耦合到FPGA，对FPGA中的多个存储单元进行块擦除，验证块擦除成功，编程 FPGA的上一页，验证上页编程是否成功，编写FPGA的下一页，并验证下页编程是否成功。

67. 发明申请

US20110014574A1 METHOD OF FORMING PITCH MULTIPLED CONTACTS 有权
标题翻译：形成拼接联系人的方法
公开(公告)号：US20110014574A1
公开(公告)日：2011-01-20
申请号：US12894633
申请日：2010-09-30
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： G03F7/20
CPC分类号： H01L21/3088 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76805 , H01L21/76816 , H01L21/76838 , H01L27/1052 , H01L27/10888 , H01L27/11521
摘要： Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. The features can have a reduced pitch in one direction and a wider pitch in another direction. Conventional photo-lithography steps can be used in combination with pitch-reduction techniques to form elongate, pitch-reduced features such as bit-line contacts, for example.
摘要翻译：公开了形成用于集成电路的导电和/或半导体特征的方法。可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。这些特征可以在一个方向上具有减小的间距，在另一方向上可以具有较宽的间距。常规的光刻步骤可以与俯仰减小技术组合使用以形成例如细长的俯仰特征，例如位线接触。

68. 发明申请

US20110008970A1 Methods of Forming Semiconductor Constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20110008970A1
公开(公告)日：2011-01-13
申请号：US12886459
申请日：2010-09-20
申请人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu , Luan C. Tran
发明人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu , Luan C. Tran
IPC分类号： H01L21/31
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/76232 , H01L27/105 , H01L27/1052
摘要： The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.
摘要翻译：本发明包括形成用于半导体结构的隔离区域的方法。可以在半导体衬底上形成并图案化硬掩模，其中图案化的硬掩模暴露衬底的区域。可以蚀刻这样的暴露区域以形成具有第一宽度的第一开口。第一个开口用含碳材料的共形层变窄。穿过保形层以沿着狭窄的开口的底部露出衬底。去除暴露的衬底以形成连接到第一开口的第二开口，并且具有小于第一宽度的第二宽度。然后从第一开口内去除含碳材料，并且电绝缘材料形成在第一和第二开口内。电绝缘材料可以基本上填充第一开口，并在第二开口内留下空隙。

69. 发明授权

US07659161B2 Methods of forming storage nodes for a DRAM array 有权
标题翻译：形成DRAM阵列的存储节点的方法
公开(公告)号：US07659161B2
公开(公告)日：2010-02-09
申请号：US11111360
申请日：2005-04-21
申请人： Luan C. Tran , Fred D. Fishburn
发明人： Luan C. Tran , Fred D. Fishburn
IPC分类号： H01L21/00
CPC分类号： H01L27/10888 , H01L27/1052 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L27/24 , Y10S257/906 , Y10S257/908
摘要： The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
摘要翻译：本发明包括可用于形成存储器阵列的存储器阵列和方法。在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

70. 发明授权

US07288806B2 DRAM arrays 有权
标题翻译： DRAM阵列
公开(公告)号：US07288806B2
公开(公告)日：2007-10-30
申请号：US11111605
申请日：2005-04-21
申请人： Luan C. Tran , Fred D. Fishburn
发明人： Luan C. Tran , Fred D. Fishburn
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10888 , H01L27/1052 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L27/24 , Y10S257/906 , Y10S257/908
摘要： The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
摘要翻译：本发明包括可用于形成存储器阵列的存储器阵列和方法。在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

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