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1. 发明授权

US08809198B2 Nano-crystal etch process 有权
标题翻译：纳米晶体蚀刻工艺
公开(公告)号：US08809198B2
公开(公告)日：2014-08-19
申请号：US12650029
申请日：2009-12-30
申请人： Ramakanth Alapati , Paul Morgan , Max Hineman
发明人： Ramakanth Alapati , Paul Morgan , Max Hineman
IPC分类号： H01L21/302
CPC分类号： H01L21/32134 , B82Y10/00 , H01L21/28273
摘要： A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing the nano-crystals to a high density plasma comprising a source of free radical chlorine, ionic chlorine, or both to modify the nano-crystals; and removing the modified nano-crystals with a wet etchant.
摘要翻译：一种用于在绝缘层上选择性去除纳米晶体的方法。该方法包括在其上提供具有纳米晶体的绝缘层; 将纳米晶体暴露于包含游离基氯源，离子氯或二者的高密度等离子体，以修饰纳米晶体; 并用湿蚀刻剂去除修饰的纳米晶体。

2. 发明授权

US08598632B2 Integrated circuit having pitch reduced patterns relative to photoithography features 失效
标题翻译：具有相对于光刻特征的节距减小图案的集成电路
公开(公告)号：US08598632B2
公开(公告)日：2013-12-03
申请号：US13530679
申请日：2012-06-22
申请人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
发明人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L27/118
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.
摘要翻译：具有不同尺寸特征的集成电路，其中较小特征与具有通过常规光刻形成的尺寸的较大特征具有间距倍增关系。

3. 发明授权

US08338959B2 Simplified pitch doubling process flow 有权
标题翻译：简化俯仰加倍流程
公开(公告)号：US08338959B2
公开(公告)日：2012-12-25
申请号：US13229898
申请日：2011-09-12
申请人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
发明人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
IPC分类号： H01L23/48
CPC分类号： H01L27/04 , H01L21/0338 , H01L21/3088 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
摘要翻译：一种用于制造半导体器件的方法包括对一层光致抗蚀剂材料进行构图以形成多个心轴。该方法还包括通过原子层沉积（ALD）工艺在多个心轴上沉积氧化物材料。该方法还包括从暴露的水平表面各向异性地蚀刻氧化物材料。该方法还包括选择性地蚀刻光刻胶材料。

4. 发明授权

US07867843B2 Gate structures for flash memory and methods of making same 有权
标题翻译：闪存的门结构及其制作方法
公开(公告)号：US07867843B2
公开(公告)日：2011-01-11
申请号：US11615321
申请日：2006-12-22
申请人： Ramakanth Alapati , Ardavan Niroomand
发明人： Ramakanth Alapati , Ardavan Niroomand
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A process may include forming a polysilicon pinnacle above and on a polysilicon island and further forming a floating gate from the polysilicon pinnacle and polysilicon island. The floating gate can bear an inverted T-shape. The floating gate can also be disposed above an isolated semiconductive substrate such as in a shallow-trench isolation semiconductive substrate. Electronic devices may include the floating gate as part of a field effect transistor.
摘要翻译：一种工艺可以包括在多晶硅岛上方和多晶硅岛上形成多晶硅巅峰，并进一步从多晶硅巅峰和多晶硅岛形成浮栅。浮动门可承受倒置的T形。浮置栅极也可以设置在隔离的半导体衬底之上，例如在浅沟槽隔离半导体衬底中。电子器件可以包括浮置栅极作为场效应晶体管的一部分。

5. 发明授权

US07737031B2 Insitu formation of inverse floating gate poly structures 有权
标题翻译：反浮栅聚结构的内部形成
公开(公告)号：US07737031B2
公开(公告)日：2010-06-15
申请号：US11832972
申请日：2007-08-02
申请人： Ramakanth Alapati , Gurtej Sandhu
发明人： Ramakanth Alapati , Gurtej Sandhu
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11521
摘要： Briefly, in accordance with one or more embodiments, a method of making an inverse-t shaped floating gate in a non-volatile memory cell or the like is disclosed.
摘要翻译：简而言之，根据一个或多个实施例，公开了在非易失性存储单元等中制作逆T形浮动栅极的方法。

6. 发明申请

US20070246795A1 Dual depth shallow trench isolation and methods to form same 审中-公开
标题翻译：双深度浅沟槽隔离和方法形成相同
公开(公告)号：US20070246795A1
公开(公告)日：2007-10-25
申请号：US11409356
申请日：2006-04-20
申请人： Xiaolong Fang , Ramakanth Alapati , Tuman Allen
发明人： Xiaolong Fang , Ramakanth Alapati , Tuman Allen
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L27/115 , H01L21/76229 , H01L27/1052 , H01L27/11526 , H01L27/11543
摘要： Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes that utilize disclosed dry etching processes to form a significant depth A between an array trench depth and a periphery trench depth. One etching method creates a trench delta depth utilizing a single dry etch step, while two other etching methods create a trench A depth by utilizing three dry etch steps.
摘要翻译：描述了用于制造半导体器件的沟槽隔离结构和形成方法。使用若干处理方案形成沟槽隔离结构，这些处理方案利用公开的干蚀刻工艺在阵列沟槽深度和外围沟槽深度之间形成显着的深度A. 一种蚀刻方法利用单次干蚀刻步骤产生沟槽三角形深度，而另外两种蚀刻方法通过利用三个干蚀刻步骤产生沟槽A深度。

7. 发明申请

US20070238295A1 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20070238295A1
公开(公告)日：2007-10-11
申请号：US11402659
申请日：2006-04-11
申请人： Ramakanth Alapati , Ardavan Niroomand , Gurtej Sandhu , Luan Tran
发明人： Ramakanth Alapati , Ardavan Niroomand , Gurtej Sandhu , Luan Tran
IPC分类号： H01L21/302 , H01L21/31
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/76232 , H01L27/105 , H01L27/1052
摘要： The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.
摘要翻译：本发明包括形成用于半导体结构的隔离区域的方法。可以在半导体衬底上形成并图案化硬掩模，其中图案化的硬掩模暴露衬底的区域。可以蚀刻这样的暴露区域以形成具有第一宽度的第一开口。第一个开口用含碳材料的共形层变窄。穿过保形层以沿着狭窄的开口的底部露出衬底。去除暴露的衬底以形成连接到第一开口的第二开口，并且具有小于第一宽度的第二宽度。然后从第一开口内去除含碳材料，并且在第一和第二开口内形成电绝缘材料。电绝缘材料可以基本上填充第一开口，并在第二开口内留下空隙。

8. 发明申请

US20140070405A1 STACKED SEMICONDUCTOR DEVICES WITH A GLASS WINDOW WAFER HAVING AN ENGINEERED COEFFICIENT OF THERMAL EXPANSION AND METHODS OF MAKING SAME 审中-公开
标题翻译：带玻璃窗的堆叠半导体器件，具有工程化的热膨胀系数及其制造方法
公开(公告)号：US20140070405A1
公开(公告)日：2014-03-13
申请号：US13613600
申请日：2012-09-13
申请人： Rahul Agarwal , Ramakanth Alapati
发明人： Rahul Agarwal , Ramakanth Alapati
IPC分类号： H01L23/498 , H01L21/50 , H01L23/48
CPC分类号： H01L24/97 , H01L21/561 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/13 , H01L23/15 , H01L23/3121 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/81 , H01L2924/00012 , H01L2224/83 , H01L2924/00
摘要： One illustrative device disclosed herein includes a device substrate having a plurality of first die formed adjacent a front side of the device substrate, a glass window wafer attached to a back side of the device substrate, wherein the glass window wafer has a plurality of openings formed therein and a coefficient of thermal expansion that is within plus or minus 200-500% of the coefficient of thermal expansion of the device wafer, and a plurality of second die, each of which is positioned in one of the openings in the glass window wafer and electrically coupled to one of the first die.
摘要翻译：本文公开的一种说明性器件包括具有邻近器件基板的前侧形成的多个第一管芯的器件衬底，附接到器件衬底背面的玻璃窗晶片，其中玻璃窗晶片具有形成的多个开口并且热膨胀系数在装置晶片的热膨胀系数的正负200-500％之内，并且多个第二模具位于玻璃窗晶片的一个开口中并且电耦合到第一管芯中的一个。

9. 发明授权

US08143167B2 Fabrication processes for forming dual depth trenches using a dry etch that deposits a polymer 有权
标题翻译：使用沉积聚合物的干蚀刻形成双深度沟槽的制造工艺
公开(公告)号：US08143167B2
公开(公告)日：2012-03-27
申请号：US12396952
申请日：2009-03-03
申请人： Xiaolong Fang , Ramakanth Alapati , Tuman E. Allen
发明人： Xiaolong Fang , Ramakanth Alapati , Tuman E. Allen
IPC分类号： H01L21/311
CPC分类号： H01L27/115 , H01L21/76229 , H01L27/1052 , H01L27/11526 , H01L27/11543
摘要： Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes that utilize disclosed dry etching processes to form a significant depth Δ between an array trench depth and a periphery trench depth. One etching method creates a trench delta depth utilizing a single dry etch step, while two other etching methods create a trench Δ depth by utilizing three dry etch steps.
摘要翻译：描述了用于制造半导体器件的沟槽隔离结构和形成方法。使用若干处理方案形成沟槽隔离结构，这些处理方案利用公开的干蚀刻工艺以形成显着的深度＆Dgr; 在阵列沟槽深度和外围沟槽深度之间。一种蚀刻方法利用单次干蚀刻步骤产生沟槽三角形深度，而另外两种蚀刻方法产生沟槽＆Dgr; 利用三个干蚀刻步骤进行深度测量。

10. 发明授权

US08048812B2 Pitch reduced patterns relative to photolithography features 有权
标题翻译：相对于光刻特征的间距减小
公开(公告)号：US08048812B2
公开(公告)日：2011-11-01
申请号：US12769071
申请日：2010-04-28
申请人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
发明人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L21/302
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.
摘要翻译：通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。间距乘法用于形成第一模式的较小特征。通过图案化无定形碳层来实现间距倍增。然后在非晶碳侧壁上形成侧壁间隔物，然后将其去除; 侧壁间隔物限定第一掩模图案。然后沉积底部抗反射涂层（BARC）以形成平坦表面，并且在BARC上形成光致抗蚀剂层。接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，其转移到BARC。将组合图案转移到下面的非晶硅层。然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。然后将组合的掩模图案蚀刻到下面的基底中。

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