专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US06864533B2 MOS field effect transistor with reduced on-resistance 有权
公开(公告)号：US06864533B2
公开(公告)日：2005-03-08
申请号：US09949646
申请日：2001-09-12
申请人： Norio Yasuhara , Akio Nakagawa , Yusuke Kawaguchi , Kazutoshi Nakamura
发明人： Norio Yasuhara , Akio Nakagawa , Yusuke Kawaguchi , Kazutoshi Nakamura
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7816 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/4175 , H01L29/41766 , H01L29/7801 , H01L29/7818 , H01L29/7824 , H01L29/7833 , H01L29/7835
摘要： A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.

62. 发明授权

US06353252B1 High breakdown voltage semiconductor device having trenched film connected to electrodes 失效
标题翻译：具有连接到电极的沟槽膜的高击穿电压半导体器件
公开(公告)号：US06353252B1
公开(公告)日：2002-03-05
申请号：US09628715
申请日：2000-07-28
申请人： Norio Yasuhara , Kazutoshi Nakamura , Yusuke Kawaguchi
发明人： Norio Yasuhara , Kazutoshi Nakamura , Yusuke Kawaguchi
IPC分类号： H01L2358
CPC分类号： H01L29/7802 , H01L21/763 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/405 , H01L29/407 , H01L29/7397 , H01L29/7824 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A plurality of trenches are formed in a drift region between a p-type body region and an-type buffer region. A silicon oxide film is formed on the side and bottom of each of the trenches, and an SIPOS film is buried into each of the trenches. The trenches are formed by RIE, and the SIPOS film is deposited by LPCVD and an undesired portion can be removed by dry etching such as RIE. The SIPOS film is connected to a source electrode at the source end of each trench, and it is connected to a drain electrode directly or through a resistor at the drain end thereof. When a high voltage is applied, a depletion layer expands in the n-type drift region from an interface between the n-type drift region and the trench on each side of the n-type drift region, therefore, the impurity concentration of the n-type drift region can be heightened without lowering the high breakdown voltage, and the resistance of the drift region can be decreased.
摘要翻译：多个沟槽形成在p型体区域和类型缓冲区域之间的漂移区域中。在每个沟槽的侧面和底部形成氧化硅膜，并且将SIPOS膜埋入每个沟槽中。沟槽由RIE形成，并且SIPOS膜通过LPCVD沉积，并且不期望的部分可以通过诸如RIE的干蚀刻来去除。 SIPOS膜在每个沟槽的源极处连接到源电极，并且在其漏极端处直接或通过电阻器连接到漏电极。当施加高电压时，耗尽层在n型漂移区域中从n型漂移区域和n型漂移区域两侧的沟槽之间的界面扩展，因此n型漂移区域的杂质浓度可以在不降低高击穿电压的情况下提高型漂移区域，并且可以减小漂移区域的电阻。

63. 发明授权

US08502305B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08502305B2
公开(公告)日：2013-08-06
申请号：US13421816
申请日：2012-03-15
申请人： Tsuyoshi Ohta , Tatsuya Nishiwaki , Norio Yasuhara , Masatoshi Arai , Takahiro Kawano
发明人： Tsuyoshi Ohta , Tatsuya Nishiwaki , Norio Yasuhara , Masatoshi Arai , Takahiro Kawano
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L21/2255 , H01L21/26586 , H01L29/0696 , H01L29/0856 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L29/861
摘要： According to an embodiment, a semiconductor device includes a semiconductor layer of a first conductive type, a base region of a second conductive type provided on the semiconductor layer and a first contact region of a second conductive type provided on the base region. The device includes a gate electrode provided in a trench piercing through the first contact region and the base region, and an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element. The device further includes a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region.
摘要翻译：根据实施例，半导体器件包括第一导电类型的半导体层，设置在半导体层上的第二导电类型的基极区域和设置在基极区域上的第二导电类型的第一接触区域。该器件包括设置在穿过第一接触区域和基极区域的沟槽中的栅电极，以及设置在栅极上并包含第一导电型杂质元素的层间绝缘膜。该器件还包括设置在层间绝缘膜和第一接触区域之间的第一导电类型的源极区域，源极区域与层间绝缘膜的侧面接触并且在基极区域中延伸。

64. 发明授权

US06720618B2 Power MOSFET device 有权
标题翻译：功率MOSFET器件
公开(公告)号：US06720618B2
公开(公告)日：2004-04-13
申请号：US10055947
申请日：2002-01-28
申请人： Yusuke Kawaguchi , Norio Yasuhara , Syotaro Ono , Shinichi Hodama , Akio Nakagawa
发明人： Yusuke Kawaguchi , Norio Yasuhara , Syotaro Ono , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L2976
CPC分类号： H01L21/26513 , H01L29/04 , H01L29/0653 , H01L29/0847 , H01L29/0878 , H01L29/1045 , H01L29/1095 , H01L29/41 , H01L29/4175 , H01L29/42372 , H01L29/42376 , H01L29/66659 , H01L29/66712 , H01L29/7802 , H01L29/7835
摘要： A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.
摘要翻译：一种功率MOSFET器件，包括第一导电类型的低电阻衬底，形成在低电阻衬底上的第一导电类型的高电阻外延层，形成在高电阻外延表面区域中的第二导电类型的基极层形成在基底层的表面区域中的第一导电类型的源极区域，形成在基极层的表面上以与源极区域接触的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，以及形成在所述高电阻外延层的与所述源极区域和所述栅极电极相反的表面上的所述第一导电类型的LDD层，其中所述LDD层和所述低电阻衬底通过所述高电阻外延层彼此连接。

65. 发明授权

US5241210A High breakdown voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5241210A
公开(公告)日：1993-08-31
申请号：US642565
申请日：1991-01-18
申请人： Akio Nakagawa , Norio Yasuhara
发明人： Akio Nakagawa , Norio Yasuhara
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861
CPC分类号： H01L29/7824 , H01L21/74 , H01L21/76264 , H01L21/76297 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286 , H01L29/402
摘要： A high breakdown voltage semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first semiconductor region formed on the first insulating film, a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region and selectively formed on a surface portion of the first semiconductor region, a third semiconductor region having an impurity concentration lower than that of the second semiconductor region and formed on the surface portion of the first semiconductor region so as to be adjacent to or near the second semiconductor region and a fourth semiconductor region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region and formed on the surface portion of the first semiconductor region so as to be outside the third semiconductor region. A fifth semiconductor region having an impurity concentration lower than that of the second or fourth semiconductor region is formed on a bottom portion of the first semiconductor region. When a reverse bias is applied between the second and fourth semiconductor regions, a depletion layer extends vertically in the first semiconductor region and laterally in the fifth semiconductor region. The applied voltage is divided in both the directions and a high breakdown voltage can be obtained.
摘要翻译：高击穿电压半导体器件包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的第一半导体区域，具有高于第一绝缘膜的杂质浓度的第一导电类型的第二半导体区域第一半导体区域，并且选择性地形成在第一半导体区域的表面部分上，第三半导体区域具有杂质浓度低于第二半导体区域的杂质浓度，并形成在第一半导体区域的表面部分上，以便邻近或在第二半导体区域附近形成杂质浓度高于第一半导体区域的第二导电类型的第四半导体区域，并且形成在第一半导体区域的表面部分上，以便在第三半导体区域的外部。在第一半导体区域的底部形成有杂质浓度低于第二或第四半导体区域的第五半导体区域。当在第二和第四半导体区域之间施加反向偏压时，耗尽层在第一半导体区域中垂直延伸并且在第五半导体区域中横向延伸。施加的电压在两个方向上被分割，并且可以获得高的击穿电压。

66. 发明授权

US08643095B2 Semiconductor transistor device and method for manufacturing same 有权
标题翻译：半导体晶体管器件及其制造方法
公开(公告)号：US08643095B2
公开(公告)日：2014-02-04
申请号：US13239248
申请日：2011-09-21
申请人： Miwako Suzuki , Norio Yasuhara
发明人： Miwako Suzuki , Norio Yasuhara
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/66734
摘要： According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer. The device includes a source layer selectively provided on a surface of the base layer. The device includes a gate electrode provided via a gate insulating film in a trench penetrating the source layer and the base layer to reach the drift layer. The device includes a field plate electrode provided under the gate electrode in the trench. The device includes a drain electrode electrically connected to the drift layer. The device includes a source electrode. The field plate electrode is electrically connected to the source electrode. An impurity concentration of a first conductivity type contained in the base layer is lower than an impurity concentration of the first conductivity type contained in the drift layer. And the impurity concentration of the first conductivity type contained in the drift layer is not less than 1×1016 (atoms/cm3).
摘要翻译：根据一个实施例，半导体器件包括漂移层。该装置包括基层。该装置包括选择性地设置在基底层的表面上的源极层。该器件包括通过栅极绝缘膜设置在穿过源极层的沟槽和基极层中以到达漂移层的栅电极。该器件包括设置在沟槽中的栅电极下方的场板电极。该器件包括电连接到漂移层的漏电极。该装置包括源电极。场极板电极与源电极电连接。包含在基底层中的第一导电类型的杂质浓度低于漂移层中包含的第一导电类型的杂质浓度。并且漂移层中所含的第一导电类型的杂质浓度不小于1×1016（原子/ cm3）。

67. 发明授权

US5689121A Insulated-gate semiconductor device 失效
标题翻译：绝缘栅半导体器件
公开(公告)号：US5689121A
公开(公告)日：1997-11-18
申请号：US480389
申请日：1995-06-07
申请人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
发明人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译：绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

68. 发明申请

US20130248995A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130248995A1
公开(公告)日：2013-09-26
申请号：US13607533
申请日：2012-09-07
申请人： Tatsuya NISHIWAKI , Tsuyoshi Ota , Norio Yasuhara , Masatoshi Arai , Takahiro Kawano
发明人： Tatsuya NISHIWAKI , Tsuyoshi Ota , Norio Yasuhara , Masatoshi Arai , Takahiro Kawano
IPC分类号： H01L29/78 , H01L21/82 , H01L27/088
CPC分类号： H01L29/7827 , H01L21/82 , H01L27/088 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/41775 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type, a base layer of a second conductivity type placed above the first semiconductor layer, a second semiconductor layer of the first conductivity type placed above the base layer, multiple gate electrodes having upper end is positioned above the upper surface of the base layer, a lower end positioned below the bottom of the base layer, and contacting the first semiconductor layer, the second semiconductor layer, and the base layer through a gate insulating film, insulating component arranged above the gate electrode in which the upper surface is positioned below the upper surface of the second semiconductor layer, and a conductive layer covering the second semiconductor layer from the upper end to the bottom end.
摘要翻译：半导体器件包括第一导电类型的第一半导体层，位于第一半导体层上方的第二导电类型的基极层，位于基极层之上的第一导电类型的第二半导体层，具有上端的多个栅电极位于所述基底层的上表面的上方，位于所述基底层的底部下方的下端，并且通过栅极绝缘膜与所述第一半导体层，所述第二半导体层和所述基底层接触，栅电极，其上表面位于第二半导体层的上表面下方，以及导电层，其从上端到底端覆盖第二半导体层。

69. 发明申请

US20120241851A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120241851A1
公开(公告)日：2012-09-27
申请号：US13239248
申请日：2011-09-21
申请人： Miwako Suzuki , Norio Yasuhara
发明人： Miwako Suzuki , Norio Yasuhara
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/66734
摘要： According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer. The device includes a source layer selectively provided on a surface of the base layer. The device includes a gate electrode provided via a gate insulating film in a trench penetrating the source layer and the base layer to reach the drift layer. The device includes a field plate electrode provided under the gate electrode in the trench. The device includes a drain electrode electrically connected to the drift layer. The device includes a source electrode. The field plate electrode is electrically connected to the source electrode. An impurity concentration of a first conductivity type contained in the base layer is lower than an impurity concentration of the first conductivity type contained in the drift layer. And the impurity concentration of the first conductivity type contained in the drift layer is not less than 1×1016 (atoms/cm3).
摘要翻译：根据一个实施例，半导体器件包括漂移层。该装置包括基层。该装置包括选择性地设置在基底层的表面上的源极层。该器件包括通过栅极绝缘膜设置在穿过源极层的沟槽和基极层中以到达漂移层的栅电极。该器件包括设置在沟槽中的栅电极下方的场板电极。该器件包括电连接到漂移层的漏电极。该装置包括源电极。场极板电极与源电极电连接。包含在基底层中的第一导电类型的杂质浓度低于漂移层中包含的第一导电类型的杂质浓度。并且漂移层中所含的第一导电类型的杂质浓度不小于1×1016（原子/ cm3）。

70. 发明授权

US5294825A High breakdown voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5294825A
公开(公告)日：1994-03-15
申请号：US753433
申请日：1991-08-30
申请人： Akio Nakagawa , Norio Yasuhara
发明人： Akio Nakagawa , Norio Yasuhara
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861
CPC分类号： H01L29/7824 , H01L21/74 , H01L21/76264 , H01L21/76297 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286 , H01L29/402
摘要： A high breakdown voltage semiconductor device is disclosed which comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a first semiconductor region formed on the first insulating layer and isolated at its side by an isolating region, a second semiconductor region of a first conductivity type formed in a surface portion of the first semiconductor region and having a higher impurity concentration than that of the first semiconductor region, a third semiconductor region of a second conductivity type formed in the surface region of the first semiconductor region such that it is located between the second semiconductor region and the isolating region in a manner to be spaced apart from the second semiconductor region, the third semiconductor region having a higher impurity concentration than that of the first semiconductor region.
摘要翻译：公开了一种高耐压电压半导体器件，其包括半导体衬底，形成在半导体衬底上的绝缘层，形成在第一绝缘层上并通过隔离区隔离的第一半导体区域，第一半导体区域导电型形成在第一半导体区域的表面部分中并且具有比第一半导体区域的杂质浓度高的第二导电类型的第三半导体区域，形成在第一半导体区域的表面区域中，使得其位于在第二半导体区域和隔离区域之间以与第二半导体区域间隔开的方式，第三半导体区域的杂质浓度高于第一半导体区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式