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61. 发明授权

US07759972B1 Integrated circuit architectures with heterogeneous high-speed serial interface circuitry 有权
标题翻译：具有异构高速串行接口电路的集成电路架构
公开(公告)号：US07759972B1
公开(公告)日：2010-07-20
申请号：US11981934
申请日：2007-10-31
申请人： Sergey Shumarayev , Wilson Wong , Weiqi Ding , Thungoc M. Tran , Tim Tri Hoang
发明人： Sergey Shumarayev , Wilson Wong , Weiqi Ding , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： An integrated circuit device such as a programmable logic device (“PLD”) includes a plurality of blocks of legacy circuitry. These legacy blocks leave at least one corner of the device unoccupied by such legacy circuitry. This at least one corner is used for relatively newly developed circuitry so as to simplify and speed the design of relatively new circuitry, to avoid having to significantly redesign any of the legacy circuitry to give the device the capabilities of the new circuitry, etc. The relatively newly developed circuitry may be high-speed serial data signal interface (“HSSI”) circuitry that is capable of operating at serial data rates faster than any legacy HSSI circuitry on the device.
摘要翻译：诸如可编程逻辑器件（“PLD”）的集成电路器件包括多个遗留电路块。这些传统块离开设备的至少一个角落，不被这种遗留电路占用。这个至少一个角用于相对新开发的电路，以便简化和加速相对新的电路的设计，以避免必须重新设计任何传统电路以给予设备新电路的能力等。相对新开发的电路可以是高速串行数据信号接口（“HSSI”）电路，其能够以比设备上的任何传统HSSI电路更快的串行数据速率工作。

62. 发明授权

US07589651B1 Flexible signal detect for programmable logic device serial interface 有权
标题翻译：灵活的信号检测可编程逻辑器件串行接口
公开(公告)号：US07589651B1
公开(公告)日：2009-09-15
申请号：US11467332
申请日：2006-08-25
申请人： Sergey Shumarayev , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Rakesh H. Patel , Wilson Wong
IPC分类号： H03M1/00
CPC分类号： H03K19/17744 , H03K19/17732
摘要： A serial interface for a programmable logic device (PLD) uses an analog-to-digital converter (ADC) in place of conventional signal detect and receiver detect circuitry. A separate ADC can be used in each receiver and each transmitter in each serial interface on the PLD. Alternatively, time division multiplexing can be used to allow the receiver and transmitter in each receiver/transmitter pair, or even multiple receiver/transmitter pairs, to share a single ADC. When none of the receiver/transmitter pairs associated with a particular ADC is being used, the ADC can be accessed for use simply as an ADC.
摘要翻译：用于可编程逻辑器件（PLD）的串行接口使用模数转换器（ADC）来代替传统的信号检测和接收器检测电路。在PLD的每个串行接口中的每个接收器和每个发射器中可以使用单独的ADC。或者，可以使用时分复用来允许每个接收机/发射机对中的接收机和发射机，或甚至多个接收机/发射机对共享单个ADC。当没有使用与特定ADC相关联的接收器/发送器对时，ADC可以被简单地用作ADC。

63. 发明授权

US07355462B1 Phase lock loop and method for operating the same 有权
标题翻译：锁相环及其操作方法
公开(公告)号：US07355462B1
公开(公告)日：2008-04-08
申请号：US11456484
申请日：2006-07-10
申请人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev
发明人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L7/093 , H03L7/18
摘要： A digital controller for a voltage controlled oscillator (VCO) is provided within a phase lock loop (PLL). The digital controller includes a digital filter having first and second inputs for receiving upward and downward adjustment signals, respectively. The digital filter generates an increment signal and a decrement signal in response to the upward and downward adjustment signals, respectively. The digital controller includes a digital counter having first and second inputs for receiving the increment and decrement signals, respectively. The digital counter generates a multi-bit output signal that represents a running sum of the increment and decrement signals. The digital controller further includes a digital-to-analog converter (DAC) having an input for receiving the running sum output signal generated by the digital counter. The DAC is defined to generate a control voltage for the VCO in response to receipt of the running sum output signal from the digital counter.
摘要翻译：在锁相环（PLL）内提供压控振荡器（VCO）的数字控制器。数字控制器包括具有分别用于接收上下调节信号的第一和第二输入的数字滤波器。数字滤波器分别响应于上下调节信号产生增量信号和减量信号。数字控制器包括一个数字计数器，它具有分别用于接收增量和减量信号的第一和第二输入端。数字计数器产生一个多位输出信号，表示增量和减量信号的运行和。数字控制器还包括具有用于接收由数字计数器产生的运行和输出信号的输入的数模转换器（DAC）。 DAC被定义为响应于来自数字计数器的运行和输出信号的接收而产生用于VCO的控制电压。

64. 发明申请

US20070025436A1 High-speed data reception circuitry and methods 有权
标题翻译：高速数据接收电路和方法
公开(公告)号：US20070025436A1
公开(公告)日：2007-02-01
申请号：US11192539
申请日：2005-07-28
申请人： Sergey Shumarayev , Wilson Wong , Rakesh Patel
发明人： Sergey Shumarayev , Wilson Wong , Rakesh Patel
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03573
摘要： Equalization circuitry for receiving a digital data signal includes both feed-forward equalizer (“FFE”) circuitry and decision-feedback equalizer (“DFE”) circuitry. The FFE circuitry may be used to give the DFE circuitry a signal that is at least minimally adequate for proper start-up of the DFE circuitry. Thereafter, more of the burden of the equalization task may be shifted from the FFE circuitry to the DFE circuitry.
摘要翻译：用于接收数字数据信号的均衡电路包括前馈均衡器（“FFE”）电路和判决反馈均衡器（“DFE”）电路。 FFE电路可以用于给DFE电路提供至少最不足以适当启动DFE电路的信号。此后，均衡任务的更多负担可能从FFE电路转移到DFE电路。

65. 发明授权

US07132847B1 Programmable slew rate control for differential output 有权
标题翻译：差分输出的可编程压摆率控制
公开(公告)号：US07132847B1
公开(公告)日：2006-11-07
申请号：US10708303
申请日：2004-02-24
申请人： Wilson Wong , Sergey Shumarayev , Rakesh Patel
发明人： Wilson Wong , Sergey Shumarayev , Rakesh Patel
IPC分类号： H03K19/003
CPC分类号： H03K17/6872 , H03K17/164
摘要： A programmable technique is used to control the slew rate of a differential output buffer. A method controls the slew rate (SR) by changing an “on” resistance of the switches used to steer the current. This can be accomplished by (i) using different size switches or (ii) changing the slew rate of the predrivers which drive the final switches. The latter approach has the advantage that it only temporarily increases the “on” resistance, which does not cause any headroom problems after the transient. A specific application is for the differential outputs of a programmable logic integrated circuits.
摘要翻译：可编程技术用于控制差分输出缓冲器的转换速率。一种方法通过改变用于转向电流的开关的“导通”电阻来控制转换速率（SR）。这可以通过（i）使用不同尺寸的开关或（ii）改变驱动最终开关的预驱动器的转换速率来实现。后一种方法的优点在于它仅暂时增加了“接通”电阻，这在瞬时之后不会引起任何余量问题。具体应用是可编程逻辑集成电路的差分输出。

66. 发明授权

US06888370B1 Dynamically adjustable termination impedance control techniques 有权
标题翻译：动态可调终端阻抗控制技术
公开(公告)号：US06888370B1
公开(公告)日：2005-05-03
申请号：US10645932
申请日：2003-08-20
申请人： Mei Luo , Wilson Wong , Sergey Shumarayev
发明人： Mei Luo , Wilson Wong , Sergey Shumarayev
IPC分类号： H03K19/0175 , H04L25/02
CPC分类号： H04L25/0278
摘要： The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.
摘要翻译：片内阻抗终端电路可以动态调节，以匹配传输线阻抗值。集成电路上的终端电阻网络为耦合到IO引脚的传输线提供终端阻抗。终端电阻器串联耦合并且彼此并联。通孔与电阻耦合。传递门单独接通或断开以将电阻与传输线耦合或去耦。每个通过门被设置为ON或OFF以向传输线提供所选择的终端电阻值。可以增加或减少电阻网络的终端电阻以匹配不同传输线路的阻抗。也可以改变终端电阻以补偿由集成电路上的温度变化或其他因素引起的电阻器的变化。

67. 发明授权

US08976804B1 Power supply filtering for programmable logic device having heterogeneous serial interface architecture 有权
标题翻译：具有异构串行接口架构的可编程逻辑器件的电源滤波
公开(公告)号：US08976804B1
公开(公告)日：2015-03-10
申请号：US13041764
申请日：2011-03-07
申请人： Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H04L12/66
CPC分类号： H03K19/17744
摘要： In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.
摘要翻译：在具有多种不同类型的串行接口的可编程逻辑器件中，不同的电源滤波方案被应用于不同的接口。对于以最低数据速率操作的接口，例如，可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。对于以较高数据速率工作的接口，例如，也可以提供3 Gbps适度的封装内滤波，这可能包括功率岛解耦。对于以更高的数据速率运行的接口，例如，也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。对于以最高数据速率工作的接口，例如，可以提供10Gbps片上滤波，其可以包括一个或多个片上滤波或调节网络。片上调节器可以可编程地旁路，允许用户权衡功能以节省功率。

68. 发明授权

US08385496B1 Apparatus and methods of receiver offset calibration 有权
标题翻译：接收机偏移校准的装置和方法
公开(公告)号：US08385496B1
公开(公告)日：2013-02-26
申请号：US12909744
申请日：2010-10-21
申请人： Allen Chan , Wilson Wong , Sergey Shumarayev
发明人： Allen Chan , Wilson Wong , Sergey Shumarayev
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H04L7/033
摘要： One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.
摘要翻译：一个实施例涉及一种用于集成电路中的接收机的偏移抵消的方法。接收机设置为相位检测器偏移消除模式，以便确定相位检测器的偏移消除设置。偏移消除设置被应用于相位检测器。然后将接收机设置为接收器 - 驱动器偏移消除模式，以便确定接收器驱动器的偏移消除设置。该偏移消除设置被应用于接收器驱动器。另一实施例涉及被配置为执行接收机偏移消除的集成电路。该集成电路包括被配置为接收差分输入信号的接收器驱动器，包括多个锁存器的相位检测器，校准控制器，电压源以及第一和第二对开关。还公开了其它实施例，方面和特征。

69. 发明授权

US08319564B2 Integrated circuits with configurable inductors 有权
标题翻译：具有可配置电感器的集成电路
公开(公告)号：US08319564B2
公开(公告)日：2012-11-27
申请号：US12748261
申请日：2010-03-26
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H03B5/12 , H03L1/00
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

70. 发明授权

US08081723B1 Serial data signal eye width estimator methods and apparatus 有权
标题翻译：串行数据信号眼宽估计方法和装置
公开(公告)号：US08081723B1
公开(公告)日：2011-12-20
申请号：US12082343
申请日：2008-04-09
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran
IPC分类号： H04L7/00
CPC分类号： H04L7/048 , H04L1/205 , H04L7/033
摘要： Methods and apparatus for determining at least part of the width of the eye of a high-speed serial data signal use clock and data recovery circuitry operating on that signal to produce a first clock signal having a first phase relationship to the data signal. The first clock signal is used to produce a second clock signal whose phase can be controllably shifted relative to the first phase. The second clock signal is used to sample the data signal with different amounts of phase shift, e.g., until error checking circuitry detects that data errors in the resulting sample exceed an acceptable threshold for such errors. The amount(s) of phase shift that caused exceeding the threshold can be used as a basis for a measurement of eye width.
摘要翻译：用于确定高速串行数据信号的眼睛的至少部分宽度的方法和装置使用在该信号上操作的时钟和数据恢复电路，以产生与数据信号具有第一相位关系的第一时钟信号。第一时钟信号用于产生第二时钟信号，其相位可相对于第一相位被可控地偏移。第二时钟信号用于以不同量的相移对数据信号进行采样，例如直到错误检查电路检测到所得样本中的数据错误超过这种错误的可接受的阈值。引起超过阈值的相移量可用作测量眼睛宽度的基础。

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