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1. 发明授权

US08290750B1 Signal detect for high-speed serial interface 有权
标题翻译：信号检测用于高速串行接口
公开(公告)号：US08290750B1
公开(公告)日：2012-10-16
申请号：US13036437
申请日：2011-02-28
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
IPC分类号： H03F1/26
CPC分类号： H03K5/19 , H03K19/1774 , H03K19/17744 , H03K19/1778
摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.
摘要翻译：串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

2. 发明申请

US20090011716A1 SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：用于可编程逻辑器件高速串行接口的信号丢失检测器
公开(公告)号：US20090011716A1
公开(公告)日：2009-01-08
申请号：US11773234
申请日：2007-07-03
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H04Q7/20
CPC分类号： H04L25/45
摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.
摘要翻译：信号丢失检测器包括对输入数据进行数字和模拟监测。输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

3. 发明申请

US20110235756A1 SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：用于可编程逻辑器件高速串行接口的信号丢失检测器
公开(公告)号：US20110235756A1
公开(公告)日：2011-09-29
申请号：US13151717
申请日：2011-06-02
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H04L27/06
CPC分类号： H04L25/45
摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.
摘要翻译：信号丢失检测器包括对输入数据进行数字和模拟监测。输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

4. 发明授权

US07759972B1 Integrated circuit architectures with heterogeneous high-speed serial interface circuitry 有权
标题翻译：具有异构高速串行接口电路的集成电路架构
公开(公告)号：US07759972B1
公开(公告)日：2010-07-20
申请号：US11981934
申请日：2007-10-31
申请人： Sergey Shumarayev , Wilson Wong , Weiqi Ding , Thungoc M. Tran , Tim Tri Hoang
发明人： Sergey Shumarayev , Wilson Wong , Weiqi Ding , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： An integrated circuit device such as a programmable logic device (“PLD”) includes a plurality of blocks of legacy circuitry. These legacy blocks leave at least one corner of the device unoccupied by such legacy circuitry. This at least one corner is used for relatively newly developed circuitry so as to simplify and speed the design of relatively new circuitry, to avoid having to significantly redesign any of the legacy circuitry to give the device the capabilities of the new circuitry, etc. The relatively newly developed circuitry may be high-speed serial data signal interface (“HSSI”) circuitry that is capable of operating at serial data rates faster than any legacy HSSI circuitry on the device.
摘要翻译：诸如可编程逻辑器件（“PLD”）的集成电路器件包括多个遗留电路块。这些传统块离开设备的至少一个角落，不被这种遗留电路占用。这个至少一个角用于相对新开发的电路，以便简化和加速相对新的电路的设计，以避免必须重新设计任何传统电路以给予设备新电路的能力等。相对新开发的电路可以是高速串行数据信号接口（“HSSI”）电路，其能够以比设备上的任何传统HSSI电路更快的串行数据速率工作。

5. 发明授权

US08127215B2 Signal loss detector for high-speed serial interface of a programmable logic device 有权
标题翻译：用于可编程逻辑器件的高速串行接口的信号丢失检测器
公开(公告)号：US08127215B2
公开(公告)日：2012-02-28
申请号：US13151717
申请日：2011-06-02
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03M13/03
CPC分类号： H04L25/45
摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.
摘要翻译：信号丢失检测器包括对输入数据进行数字和模拟监测。输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

6. 发明授权

US08081723B1 Serial data signal eye width estimator methods and apparatus 有权
标题翻译：串行数据信号眼宽估计方法和装置
公开(公告)号：US08081723B1
公开(公告)日：2011-12-20
申请号：US12082343
申请日：2008-04-09
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran
IPC分类号： H04L7/00
CPC分类号： H04L7/048 , H04L1/205 , H04L7/033
摘要： Methods and apparatus for determining at least part of the width of the eye of a high-speed serial data signal use clock and data recovery circuitry operating on that signal to produce a first clock signal having a first phase relationship to the data signal. The first clock signal is used to produce a second clock signal whose phase can be controllably shifted relative to the first phase. The second clock signal is used to sample the data signal with different amounts of phase shift, e.g., until error checking circuitry detects that data errors in the resulting sample exceed an acceptable threshold for such errors. The amount(s) of phase shift that caused exceeding the threshold can be used as a basis for a measurement of eye width.
摘要翻译：用于确定高速串行数据信号的眼睛的至少部分宽度的方法和装置使用在该信号上操作的时钟和数据恢复电路，以产生与数据信号具有第一相位关系的第一时钟信号。第一时钟信号用于产生第二时钟信号，其相位可相对于第一相位被可控地偏移。第二时钟信号用于以不同量的相移对数据信号进行采样，例如直到错误检查电路检测到所得样本中的数据错误超过这种错误的可接受的阈值。引起超过阈值的相移量可用作测量眼睛宽度的基础。

7. 发明授权

US07996749B2 Signal loss detector for high-speed serial interface of a programmable logic device 有权
标题翻译：用于可编程逻辑器件的高速串行接口的信号丢失检测器
公开(公告)号：US07996749B2
公开(公告)日：2011-08-09
申请号：US11773234
申请日：2007-07-03
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03M13/03
CPC分类号： H04L25/45
摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.
摘要翻译：信号丢失检测器包括对输入数据进行数字和模拟监测。输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

8. 发明授权

US08126079B1 High-speed serial data signal interface circuitry with multi-data-rate switching capability 有权
标题翻译：具有多数据速率切换功能的高速串行数据信号接口电路
公开(公告)号：US08126079B1
公开(公告)日：2012-02-28
申请号：US11824862
申请日：2007-07-03
申请人： Thungoc M. Tran , Sergey Shumarayev , Tim Tri Hoang , Weiqi Ding , Wilson Wong , Allen Chan
发明人： Thungoc M. Tran , Sergey Shumarayev , Tim Tri Hoang , Weiqi Ding , Wilson Wong , Allen Chan
IPC分类号： H04L27/00
CPC分类号： H04L7/033 , H03L7/22 , H04L7/0008
摘要： High-speed serial data signal transmitter and/or receiver circuitry is able to dynamically switch between handling data at two (or more) different data rates. Such a switch can be made very rapidly and with no requirement for reprogramming or reconfiguring the circuitry. Circuitry for glitchlessly switching between clock signals having different frequencies is also provided and may be used in the above-mentioned transmitter and/or receiver circuitry.
摘要翻译：高速串行数据信号发射机和/或接收机电路能够以两种（或多种）不同的数据速率在处理数据之间动态切换。这样的开关可以非常快速地进行，并且不需要重新编程或重新配置电路。还提供了用于在具有不同频率的时钟信号之间无差错地切换的电路，并且可以在上述发射机和/或接收机电路中使用。

9. 发明授权

US07899649B1 Signal detect for high-speed serial interface 有权
标题翻译：信号检测用于高速串行接口
公开(公告)号：US07899649B1
公开(公告)日：2011-03-01
申请号：US12053884
申请日：2008-03-24
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
IPC分类号： G06F19/00
CPC分类号： H03K5/19 , H03K19/1774 , H03K19/17744 , H03K19/1778
摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.
摘要翻译：串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

10. 发明授权

US08705602B1 Equalizer circuitry with selectable tap positions and coefficients 有权
标题翻译：均衡器电路，具有可选择的抽头位置和系数
公开(公告)号：US08705602B1
公开(公告)日：2014-04-22
申请号：US12580587
申请日：2009-10-16
申请人： Weiqi Ding , Mengchi Liu , Mingde Pan , Thungoc M. Tran , Sergey Shumarayev
发明人： Weiqi Ding , Mengchi Liu , Mingde Pan , Thungoc M. Tran , Sergey Shumarayev
IPC分类号： H03H7/30 , H03H7/40
CPC分类号： H04L25/03038 , H04L25/03343
摘要： Transmitter equalizer circuitry, e.g., for a serial, digital, data signal, includes tapped delay line circuitry for outputting a plurality of differently delayed versions of the signal propagating through the delay line circuitry. The equalizer circuitry also includes a plurality of electrical current digital-to-analog converters (“DACs”). The equalizer circuitry still further includes controllable (e.g., programmable) routing circuitry for selectably routing the delayed versions of the signal to the various DACs. The current strengths employed by the various DACs are also preferably controllable (e.g., programmable).
摘要翻译：例如，用于串行数字数据信号的发射机均衡器电路包括用于输出通过延迟线电路传播的信号的多个不同延迟版本的抽头延迟线电路。均衡器电路还包括多个电流数模转换器（“DAC”）。均衡器电路还包括可控（例如，可编程）路由电路，用于可选地将信号的延迟版本路由到各种DAC。各种DAC所使用的电流强度也优选是可控的（例如，可编程的）。

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