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61. 发明授权

US06400030B1 Self-aligning vias for semiconductors 有权
标题翻译：半导体自对准通孔
公开(公告)号：US06400030B1
公开(公告)日：2002-06-04
申请号：US09583817
申请日：2000-05-30
申请人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
发明人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
IPC分类号： H01L2348
CPC分类号： H01L21/76897 , H01L21/76802
摘要： An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. The stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.
摘要翻译：具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。阻挡氮化物层以矩形通孔结构进行氮化蚀刻，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

62. 发明授权

US06399480B1 Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction 有权
标题翻译：用于绝缘局部互连的方法和布置，以改善对准公差和减小尺寸
公开(公告)号：US06399480B1
公开(公告)日：2002-06-04
申请号：US09515319
申请日：2000-02-29
申请人： William G. En , Darin A. Chan , David K. Foote , Fei Wang , Minh Van Ngo
发明人： William G. En , Darin A. Chan , David K. Foote , Fei Wang , Minh Van Ngo
IPC分类号： H01L714263
CPC分类号： H01L21/76895 , H01L21/76897
摘要： At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting,the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.
摘要翻译：在晶体管布置内提供至少一个图案化的介电层，以防止局部互连在形成局部互连的蚀刻开口的镶嵌层形成期间由于不对准导致栅极导体电接触。通过在局部互连蚀刻工艺期间通过选择性蚀刻穿过多个电介质层，将图案化的介电层留在原位以防止栅极短路到相邻的局部互连，其稍微错位。

63. 发明授权

US06380091B1 Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer 有权
标题翻译：用于与氧化物介电层和低K介电常数层的金属互连的双镶嵌布置
公开(公告)号：US06380091B1
公开(公告)日：2002-04-30
申请号：US09238050
申请日：1999-01-27
申请人： Fei Wang , Jerry Cheng , Darrell M. Erb
发明人： Fei Wang , Jerry Cheng , Darrell M. Erb
IPC分类号： H01L213065
CPC分类号： H01L21/76807 , H01L21/31116 , H01L2221/1036
摘要： A method of forming a dual damascene structure in a semiconductor device arrangement forms a first dielectric layer made of an oxide dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first dielectric layer, and a second dielectric layer, made of low k dielectric material, is formed on the nitride etch stop layer. A via is etched into the first dielectric layer, and a trench is then etched into the second dielectric layer. The materials if the first and second dielectric layers are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second dielectric layer and not the first dielectric layer.
摘要翻译：在半导体器件布置中形成双镶嵌结构的方法在诸如铜互连层的下面的金属互连层上形成由氧化物介电材料制成的第一介电层。在第一电介质层上形成氮化物蚀刻停止层，在氮化物蚀刻停止层上形成由低k电介质材料制成的第二电介质层。将通孔蚀刻到第一介电层中，然后将沟槽蚀刻到第二介电层中。如果第一和第二电介质层彼此不同，那么材料使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。因此，在蚀刻第二电介质层中的沟槽的过程中，通过采用只蚀刻第二电介质层而不是第一介电层的蚀刻化学法来防止在第一电介质层中的底切。

64. 发明授权

US06376308B1 Process for fabricating an EEPROM device having a pocket substrate region 有权
标题翻译：用于制造具有袋基底区域的EEPROM器件的工艺
公开(公告)号：US06376308B1
公开(公告)日：2002-04-23
申请号：US09487073
申请日：2000-01-19
申请人： Fei Wang , David K. Foote , Bharath Rangarajan , George Kluth
发明人： Fei Wang , David K. Foote , Bharath Rangarajan , George Kluth
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： A process for fabricating an EEPROM device having pocket substrate regions includes forming a pattern composite layer overlying a principal surface of a semiconductor substrate. The pattern composite layer includes a dielectric layer and a resist layer overlying the dielectric layer. Processing is carried out to reduce the lateral dimension of the resist layer relative to the dielectric layer thereby exposing an upper surface of the dielectric layer. A doping process is carried out in which dopants penetrate the exposed upper surface of the dielectric layer and enter the semiconductor substrate immediately below the exposed upper surface of the dielectric layer. Upon conforming the pocket regions, an oxidation process is carried out to form bit-line oxide regions in the semiconductor substrate.
摘要翻译：一种用于制造具有袋基底区域的EEPROM器件的工艺包括形成覆盖在半导体衬底的主表面上的图案复合层。图案复合层包括介电层和覆盖电介质层的抗蚀剂层。进行处理以减小抗蚀剂层相对于电介质层的横向尺寸，从而暴露电介质层的上表面。进行掺杂工艺，其中掺杂剂穿透介电层的暴露的上表面并进入电介质层暴露的上表面正下方的半导体衬底。在使袋区域一致时，进行氧化处理以在半导体衬底中形成位线氧化物区域。

65. 发明授权

US06355575B1 Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern 有权
标题翻译：半导体器件和制造方法，不会损坏HSQ层和金属图案
公开(公告)号：US06355575B1
公开(公告)日：2002-03-12
申请号：US09575463
申请日：2000-05-22
申请人： Fei Wang , Simon S. Chan , Susan Chen
发明人： Fei Wang , Simon S. Chan , Susan Chen
IPC分类号： H01L21302
CPC分类号： H01L21/76802 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： HSQ is employed as a dielectric layer in manufacturing a high density, multi-metal layer semiconductor device. The degradation of deposited HSQ layers during formation of the semiconductor device, as from photoresist stripping using an O2-containing plasma, is avoided by forming first and second dielectric layers on the HSQ layer, forming a photoresist mask on the second dielectric layer and etching to form an opening in the second dielectric layer leaving the first dielectric layer exposed. The first dielectric layer protects the HSQ from degradation during subsequent stripping.
摘要翻译： HSQ用作制造高密度多金属层半导体器件的介电层。通过在HSQ层上形成第一和第二电介质层，在第二电介质层上形成光致抗蚀剂掩模并蚀刻到第二介电层上，避免了在形成半导体器件期间沉积的HSQ层的退化，如使用含O 2等离子体的光致抗蚀剂剥离在第二电介质层中形成开口，离开第一电介质层。第一电介质层在随后的剥离过程中保护HSQ免于降解。

66. 发明授权

US06348406B1 Method for using a low dielectric constant layer as a semiconductor anti-reflective coating 有权
标题翻译：使用低介电常数层作为半导体抗反射涂层的方法
公开(公告)号：US06348406B1
公开(公告)日：2002-02-19
申请号：US09586264
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
发明人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
IPC分类号： H01L214763
CPC分类号： H01L27/11521 , H01L21/31144
摘要： The present invention provides a method for manufacturing a semiconductor device with an anti-reflective coating (ARC) that does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. A dielectric layer is then deposited over the electrical devices and the semiconductor substrate, upon which an optically transparent ARC layer of low dielectric constant is then deposited. Photoresist is then deposited on top of the ARC layer and is then photolithographically processed and subsequently developed. The dielectric layer is then etched down to the semiconductor substrate to form contacts or local interconnects. The ARC layer can subsequently be used as a hard mask and does not require removal.
摘要翻译：本发明提供一种制造具有不需要去除的抗反射涂层（ARC）的半导体器件的方法。在一个实施例中，电子器件形成在半导体衬底上。然后将电介质层沉积在电气器件和半导体衬底上，然后沉积出具有低介电常数的光学透明ARC层。然后将光致抗蚀剂沉积在ARC层的顶部上，然后光刻加工并随后显影。然后将电介质层向下蚀刻到半导体衬底以形成接触或局部互连。 ARC层可以随后用作硬掩模，并且不需要去除。

67. 发明授权

US06348379B1 Method of forming self-aligned contacts using consumable spacers 有权
标题翻译：使用可消耗隔离物形成自对准触点的方法
公开(公告)号：US06348379B1
公开(公告)日：2002-02-19
申请号：US09502153
申请日：2000-02-11
申请人： Fei Wang , Ramkumar Subramanian , Yu Sun
发明人： Fei Wang , Ramkumar Subramanian , Yu Sun
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L2924/3011
摘要： A method for shrinking a semiconductor device is disclosed. An etch stop layer is eliminated and is replaced with a consumable second sidewall spacers so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. In a preferred embodiment, the present invention provides a method for forming self-aligned contacts by forming multi-layer structures on a region on a semiconductor substrate, forming first sidewall spacers around the multi-layer structures, forming second sidewall spacers around the first sidewall spacers, forming a dielectric layer directly over the substrate and in contact with second sidewall spacers, forming an opening in the dielectric layer to expose a portion of the region on the semiconductor substrate adjacent the second sidewall spacers, and filling the opening with a conductive material to form a contact.
摘要翻译：公开了一种用于收缩半导体器件的方法。消除了蚀刻停止层，并且被可消耗的第二侧壁间隔物代替，使得该器件的堆叠栅极结构可以更靠近地放置在一起，从而允许器件收缩。在优选实施例中，本发明提供了一种通过在半导体衬底上的区域上形成多层结构来形成自对准接触的方法，在多层结构周围形成第一侧墙，围绕第一侧壁形成第二侧壁间隔物，直接在衬底上形成电介质层并与第二侧壁间隔物接触，在电介质层中形成开口以暴露与第二侧壁间隔物相邻的半导体衬底上的区域的一部分，并用导电材料填充该开口形成联系。

68. 发明授权

US06312874B1 Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials 有权
标题翻译：在低介电常数材料中形成双镶嵌沟槽和下面的无边界通孔的方法
公开(公告)号：US06312874B1
公开(公告)日：2001-11-06
申请号：US09187232
申请日：1998-11-06
申请人： Simon S. Chan , Fei Wang , Todd Lukanc
发明人： Simon S. Chan , Fei Wang , Todd Lukanc
IPC分类号： G03C500
CPC分类号： H01L21/76811 , H01L21/0332 , H01L21/31116 , H01L21/31144 , H01L21/7681 , H01L21/76813
摘要： A method of forming a dual damascene structure in low k dielectric material employs a multiple layer hard mask over the low k dielectric layer. The trench pattern is etched into the hard mask layer, followed by etching of a via pattern. The trench pattern is widened to completely coincide with the via if the via does not fall completely within the trench pattern due to alignment errors. The low dielectric constant material is protected from the photoresist removal process during the patterning and initial formation of the trench and via in the multiple layer hard mask.
摘要翻译：在低k电介质材料中形成双镶嵌结构的方法在低k电介质层上采用多层硬掩模。将沟槽图案蚀刻到硬掩模层中，随后蚀刻通孔图案。如果由于对准误差，如果通孔不完全落在沟槽图案内，则沟槽图案被加宽以与通孔完全重合。在多层硬掩模中的沟槽和通孔的图案化和初始形成期间，低介电常数材料被保护以防止光致抗蚀剂去除工艺。

69. 发明授权

US06309955B1 Method for using a CVD organic barc as a hard mask during via etch 有权
标题翻译：在通孔蚀刻期间使用CVD有机棒材作为硬掩模的方法
公开(公告)号：US06309955B1
公开(公告)日：2001-10-30
申请号：US09784065
申请日：2001-02-16
申请人： Ramkumar Subramanian , Fei Wang , Todd P. Lukanc , Lynne A. Okada
发明人： Ramkumar Subramanian , Fei Wang , Todd P. Lukanc , Lynne A. Okada
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： A method for forming a via of a metal interconnect structure in a semiconductor device employs a CVD organic BARC between a low k dielectric material and a via photoresist mask. The CVD organic BARC is deposited over the low k dielectric film and protects the film during formation and patterning of the via photoresist mask. Furthermore, the presence of the BARC permits the photoresist mask to be thinner than that used in conventional techniques thereby improving lithography resolution.
摘要翻译：在半导体器件中形成金属互连结构的通孔的方法在低k电介质材料和通孔光致抗蚀剂掩模之间采用CVD有机BARC。 CVD有机BARC沉积在低k电介质膜上，并在通孔光致抗蚀剂掩模的形成和图案化期间保护膜。此外，BARC的存在允许光致抗蚀剂掩模比常规技术中使用的光刻胶掩模更薄，从而提高光刻分辨率。

70. 发明授权

US06255735B1 Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers 有权
标题翻译：用于在电介质层中与低k介电常数材料进行金属互连的双镶嵌布置
公开(公告)号：US06255735B1
公开(公告)日：2001-07-03
申请号：US09225542
申请日：1999-01-05
申请人： Fei Wang , Jerry Cheng , Simon S. Chan , Todd Lukanc
发明人： Fei Wang , Jerry Cheng , Simon S. Chan , Todd Lukanc
IPC分类号： H01L2348
CPC分类号： H01L23/53228 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A second low k dielectric layer is formed on the first low k dielectric layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Further etching of the first dielectric layer is prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.
摘要翻译：在半导体器件布置中形成双镶嵌结构的方法在下面的金属互连层（例如铜互连层）上形成第一低k电介质材料。在第一低k电介质层上形成第二低k电介质层。将通孔蚀刻到第一低k电介质层中，然后将沟槽蚀刻到第二低k电介质层中。第一和第二低k电介质材料彼此不同，使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。在蚀刻第二电介质层中的沟槽期间，通过采用蚀刻仅蚀刻第二低k电介质材料而不是第一低k电介质材料的蚀刻化学品来防止第一电介质层的进一步腐蚀。

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