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1. 发明授权

US06380091B1 Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer 有权
标题翻译：用于与氧化物介电层和低K介电常数层的金属互连的双镶嵌布置
公开(公告)号：US06380091B1
公开(公告)日：2002-04-30
申请号：US09238050
申请日：1999-01-27
申请人： Fei Wang , Jerry Cheng , Darrell M. Erb
发明人： Fei Wang , Jerry Cheng , Darrell M. Erb
IPC分类号： H01L213065
CPC分类号： H01L21/76807 , H01L21/31116 , H01L2221/1036
摘要： A method of forming a dual damascene structure in a semiconductor device arrangement forms a first dielectric layer made of an oxide dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first dielectric layer, and a second dielectric layer, made of low k dielectric material, is formed on the nitride etch stop layer. A via is etched into the first dielectric layer, and a trench is then etched into the second dielectric layer. The materials if the first and second dielectric layers are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second dielectric layer and not the first dielectric layer.
摘要翻译：在半导体器件布置中形成双镶嵌结构的方法在诸如铜互连层的下面的金属互连层上形成由氧化物介电材料制成的第一介电层。在第一电介质层上形成氮化物蚀刻停止层，在氮化物蚀刻停止层上形成由低k电介质材料制成的第二电介质层。将通孔蚀刻到第一介电层中，然后将沟槽蚀刻到第二介电层中。如果第一和第二电介质层彼此不同，那么材料使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。因此，在蚀刻第二电介质层中的沟槽的过程中，通过采用只蚀刻第二电介质层而不是第一介电层的蚀刻化学法来防止在第一电介质层中的底切。

2. 发明授权

US06207577B1 Self-aligned dual damascene arrangement for metal interconnection with oxide dielectric layer and low k dielectric constant layer 有权
标题翻译：用于与氧化物介电层和低k介电常数层的金属互连的自对准双镶嵌布置
公开(公告)号：US06207577B1
公开(公告)日：2001-03-27
申请号：US09238049
申请日：1999-01-27
申请人： Fei Wang , Jerry Cheng , Darrell M. Erb
发明人： Fei Wang , Jerry Cheng , Darrell M. Erb
IPC分类号： H01L213065
CPC分类号： H01L21/7681 , H01L21/31138 , H01L2221/1036
摘要： A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms an oxide dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the oxide dielectric layer, and a low k dielectric layer is formed on the nitride etch stop layer. A trench is etched into the low k dielectric layer, followed by the etching of a via into the oxide dielectric layer. The oxide dielectric material and low k dielectric material are selected so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the oxide dielectric material and not the low k dielectric material.
摘要翻译：在半导体器件布置中形成自对准双镶嵌结构的方法在诸如铜互连层的下面的金属互连层之上形成氧化物介电材料。在氧化物介电层上形成氮化物蚀刻停止层，在氮化物蚀刻停止层上形成低k电介质层。将沟槽蚀刻到低k电介质层中，然后将通孔蚀刻到氧化物介电层中。选择氧化物介电材料和低k电介质材料使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。因此，在蚀刻第二电介质层中的通孔时，通过采用仅蚀刻氧化物电介质材料而不是低k电介质材料的蚀刻化学品来防止由过蚀蚀引起的第二电介质层中的底切。

3. 发明授权

US06454916B1 Selective electroplating with direct contact chemical polishing 失效
标题翻译：选择性电镀与直接接触化学抛光
公开(公告)号：US06454916B1
公开(公告)日：2002-09-24
申请号：US09477810
申请日：2000-01-05
申请人： Fei Wang , Steven C. Avanzino , Darrell M. Erb
发明人： Fei Wang , Steven C. Avanzino , Darrell M. Erb
IPC分类号： C25D1700
CPC分类号： C25D5/22 , B23H5/08 , C25D7/12 , C25D17/001
摘要： A deposition tool and a method for depositing a material within the recesses in a substrate of semiconductor wafer employs a rotatable diffuser that diffuses the plating material onto the top surface of a substrate. The diffuser is placed into contact with the semiconductor wafer and rotated while the plating material is applied through apertures in the diffuser. The plating material fills recesses patterned into the substrate of the semiconductor wafer but is prevented from forming to a significant degree on the top surface of the semiconductor wafer due to the contact and rotation of the diffuser. Since the plating material is not deposited on the top surface of the semiconductor wafer to any significant degree, chemical mechanical polishing (CMP) planarization is significantly reduced or completely eliminated.
摘要翻译：沉积工具和用于在半导体晶片的衬底内的凹槽内沉积材料的方法采用将电镀材料扩散到衬底顶表面上的可旋转漫射器。扩散器被放置成与半导体晶片接触并且当电镀材料通过扩散器中的孔施加时旋转。电镀材料填充图案化到半导体晶片的衬底中的凹槽，但是由于扩散器的接触和旋转，防止了在半导体晶片的顶表面上形成很大程度。由于电镀材料没有以任何显着的程度沉积在半导体晶片的顶表面上，所以化学机械抛光（CMP）平面化被显着地减少或完全消除。

4. 发明授权

US06319834B1 Method and apparatus for improved planarity metallization by electroplating and CMP 有权
标题翻译：通过电镀和CMP改善平面度金属化的方法和装置
公开(公告)号：US06319834B1
公开(公告)日：2001-11-20
申请号：US09639812
申请日：2000-08-17
申请人： Darrell M. Erb , Steven C. Avanzino , Fei Wang
发明人： Darrell M. Erb , Steven C. Avanzino , Fei Wang
IPC分类号： H01L2144
CPC分类号： H01L21/3212 , H01L21/2885 , H01L21/7684 , H01L21/76877 , H01L21/76879
摘要： A pattern of in-laid conductors is formed by a method utilizing electroplating and chemical-mechanical polishing (CMP). Embodiments include a first step of selectively filling recesses formed in the surface of a substrate with a metal by localized electroplating at a reduced thickness, planar-surfaced overburden or blanket layer thereon, and planarizing the surface by CMP utilizing a relatively soft CMP pad. Embodiments also include an apparatus comprising a porous pad applicator for selectively electroplating recesses formed in the surface of a workpiece.
摘要翻译：通过使用电镀和化学机械抛光（CMP）的方法形成嵌入导体的图案。实施例包括第一步骤，通过局部电镀在其上以薄的局部电镀，平面表面覆盖层或覆盖层选择性地填充形成在衬底的表面中的凹陷，并且通过使用相对较软的CMP衬垫的CMP来平坦化表面。实施例还包括一种包括用于选择性地电镀在工件表面中形成的凹槽的多孔垫施加器的装置。

5. 发明授权

US07132363B2 Stabilizing fluorine etching of low-k materials 失效
标题翻译：稳定低k材料的氟蚀刻
公开(公告)号：US07132363B2
公开(公告)日：2006-11-07
申请号：US09817056
申请日：2001-03-27
申请人： Kai Yang , Darrell M. Erb , Fei Wang
发明人： Kai Yang , Darrell M. Erb , Fei Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： Damascene processing is implemented with dielectric barrier films (50, 90, 91) for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films (50, 31) to avoid misalignment problems. Embodiments further include dual damascene (100A, 100B) processing using Cu metallization (100).
摘要翻译：用电介质阻挡膜（50,90,91）实现镶嵌加工，以改善台阶覆盖和降低的接触电阻。实施例包括使用两种不同的介电膜（50,31）来避免不对准问题。实施例还包括使用Cu金属化（100）的双镶嵌（100A，100B）处理。

6. 发明授权

US06756303B1 Diffusion barrier and method for its production 失效
标题翻译：扩散屏障及其生产方法
公开(公告)号：US06756303B1
公开(公告)日：2004-06-29
申请号：US10334361
申请日：2002-12-30
申请人： Darrell M. Erb , Fei Wang
发明人： Darrell M. Erb , Fei Wang
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76846 , H01L21/76859
摘要： A conductive diffusion barrier surrounding a conductive element is enhanced by an implanted diffusion barrier enhancing material. The enhancing material is implanted using a low energy implant at an angle to the substrate, such that the portion of the diffusion barrier at the bottom of the conductive element is protected during implantation. This prevents the increased resistivity caused by the enhancing material from affecting the conductive path between the conductive element and another conductive element. The diffusion barrier is preferably titanium nitride (TiN) and the enhancing material is preferably silicon (Si).
摘要翻译：通过植入的扩散阻挡增强材料来增强围绕导电元件的导电扩散阻挡层。使用与衬底成一定角度的低能量注入来注入增强材料，使得在植入期间保护导电元件底部的扩散阻挡层的部分被保护。这防止由增强材料引起的增加的电阻影响导电元件和另一导电元件之间的导电路径。扩散阻挡层优选为氮化钛（TiN），增强材料优选为硅（Si）。

7. 发明授权

US06465889B1 Silicon carbide barc in dual damascene processing 有权
标题翻译：碳化硅棒在双镶嵌加工
公开(公告)号：US06465889B1
公开(公告)日：2002-10-15
申请号：US09778109
申请日：2001-02-07
申请人： Ramkumar Subramanian , Fei Wang , Lynne A. Okada , Calvin T. Gabriel , Darrell M. Erb
发明人： Ramkumar Subramanian , Fei Wang , Lynne A. Okada , Calvin T. Gabriel , Darrell M. Erb
IPC分类号： H01L2348
CPC分类号： H01L21/76808 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The dimensional accuracy of trenches and, hence, the width of metal lines, in damascene interconnection structures is improved by employing silicon carbide as a capping layer/BARC on an underlying metal feature, e.g., Cu. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide capping layer/BARC having an extinction coefficient (k) of about −0.2 to about −0.5, without the need for a middle etch stop layer, thereby improving efficiency by reducing the number of processing steps.
摘要翻译：通过在下面的金属特征例如Cu上使用碳化硅作为覆盖层/ BARC来改善镶嵌互连结构中的沟槽的尺寸精度以及因此的金属线的宽度。实施例包括采用采用碳消耗系数（k）约-0.2至约-0.5的碳化硅覆盖层/ BARC的第一沟槽最后双镶嵌技术，而不需要中间蚀刻停止层，从而通过减少处理步骤数

8. 发明授权

US06768204B1 Self-aligned conductive plugs in a semiconductor device 有权
标题翻译：半导体器件中的自对准导电插头
公开(公告)号：US06768204B1
公开(公告)日：2004-07-27
申请号：US09826185
申请日：2001-04-05
申请人： Todd P. Lukanc , Fei Wang , Darrell M. Erb
发明人： Todd P. Lukanc , Fei Wang , Darrell M. Erb
IPC分类号： H01L2348
CPC分类号： H01L23/53295 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides for improved alignment of an opening in a lower dielectric layer with an opening in an upper dielectric layer. This improved alignment is beneficial as it improves the functionality of devices with dual damascene material arrangements, as normal misalignments do not deem the devices inferior or non-functional. Further, the present invention is beneficial as it allows for a designer, such as a microprocessor designer, to depend on more predictable conductive characteristics of contacts between a first conductive region and a second conductive region.
摘要翻译：本发明提供了将下介电层中的开口与上电介质层中的开口对准的改进。这种改进的对准是有益的，因为它改善了具有双镶嵌材料布置的装置的功能，因为正常的对准不认为装置较差或不起作用。此外，本发明是有益的，因为其允许诸如微处理器设计者的设计者依赖于第一导电区域和第二导电区域之间的接触的更可预测的导电特性。

9. 发明授权

US06235628B1 Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer 有权
标题翻译：形成用于具有低k介电常数材料和氧化物中间蚀刻停止层的金属互连的双镶嵌布置的方法
公开(公告)号：US06235628B1
公开(公告)日：2001-05-22
申请号：US09225545
申请日：1999-01-05
申请人： Fei Wang , Jerry Cheng
发明人： Fei Wang , Jerry Cheng
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76807
摘要： A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. An oxide etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the oxide etch stop layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.
摘要翻译：在半导体器件布置中形成双镶嵌结构的方法在下面的金属互连层（例如铜互连层）上形成第一低k电介质材料。在第一低k电介质层上形成氧化物蚀刻停止层，在氧化物蚀刻停止层上形成第二低k电介质层。将通孔蚀刻到第一低k电介质层中，然后将沟槽蚀刻到第二低k电介质层中。第一和第二低k电介质材料彼此不同，使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。因此，在蚀刻第二介质层中沟槽的过程中，通过采用只刻蚀第二低k电介质材料而不是第一低k电介质材料的蚀刻化学法来防止第一介质层中的底切。

10. 发明授权

US6107208A Nitride etch using N.sub.2 /Ar/CHF.sub.3 chemistry 失效
标题翻译：氮化物蚀刻使用N2 / Ar / CHF3化学
公开(公告)号：US6107208A
公开(公告)日：2000-08-22
申请号：US90670
申请日：1998-06-04
申请人： Jerry Cheng , Fei Wang
发明人： Jerry Cheng , Fei Wang
IPC分类号： H01L21/311 , H01L21/768 , H01L23/532 , H01L21/05
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/76829 , H01L23/53233 , H01L23/53238 , H01L2924/0002
摘要： In one embodiment, the present invention relates to a method of etching silicon nitride disposed over a copper containing layer by etching at least a portion of the silicon nitride using a nitride etch gas mixture comprising from about 5 sccm to about 15 sccm of CHF.sub.3, about 5 sccm to about 15 sccm of nitrogen and about 80 sccm to about 120 sccm of a carrier gas. In another embodiment, the present invention relates to a method of processing a semiconductor substrate comprising silicon nitride disposed over a copper containing layer, involving etching at least a portion of the silicon nitride using a nitride etch gas mixture comprising CHF.sub.3, nitrogen and Ar.
摘要翻译：在一个实施例中，本发明涉及一种通过使用包含约5sccm至约15sccm的CHF 3的氮化物蚀刻气体混合物蚀刻至少一部分氮化硅而蚀刻设置在含铜层上方的氮化硅的方法，约 5sccm至约15sccm的氮气和约80sccm至约120sccm的载气。在另一个实施例中，本发明涉及一种处理半导体衬底的方法，该半导体衬底包括设置在含铜层上的氮化硅，包括使用包含CHF 3，氮和Ar的氮化物蚀刻气体混合物蚀刻至少一部分氮化硅。

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