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    • 1. 发明申请
    • SYSTEM, METHOD AND APPARATUS FOR SEARCHING GEOGRAPHIC AREA USING PRIORITIZED SPATIAL ORDER
    • 使用优先空间订单搜索地理区域的系统,方法和设备
    • US20080103691A1
    • 2008-05-01
    • US11965525
    • 2007-12-27
    • Susan ChenClayton Barber
    • Susan ChenClayton Barber
    • G01C21/00G01C21/10
    • G01C5/005G01C23/00
    • A spatial data search method, system and apparatus for identifying particular data of significance around a reference vector through the spatial data. The method involves determining a reference vector within a spatial region for which spatial data exists, loading a portion of the spatial data including the data around the reference vector into a memory buffer, and searching the spatial data in a prioritized order. The method, system and apparatus have particular utility in searching geographic data for a terrain awareness and warning system (“TAWS”) and display in an aircraft. Embodiments of the present invention provide advantages over existing sequential and radial search methods, significantly reducing the processing and calculations required and providing faster alerts to pilots.
    • 一种用于通过空间数据识别围绕参考矢量的特定数据的空间数据搜索方法,系统和装置。 该方法包括确定存在空间数据的空间区域内的参考矢量,将包括参考矢量周围的数据的空间数据的一部分加载到存储器缓冲器中,以优先顺序搜索空间数据。 该方法,系统和装置在搜索地形数据的地形识别和警告系统(“TAWS”)并在飞行器中显示具有特殊的用途。 本发明的实施例提供了优于现有的顺序和径向搜索方法的优点,显着地减少了所需的处理和计算,并向飞行员提供了更快的警报。
    • 6. 发明授权
    • Use of hard masks during etching of openings in integrated circuits for
high etch selectivity
    • 在蚀刻集成电路中的开口处使用硬掩模以获得高蚀刻选择性
    • US6054384A
    • 2000-04-25
    • US81196
    • 1998-05-19
    • Fei WangSusan Chen
    • Fei WangSusan Chen
    • H01L21/768H01L21/4763
    • H01L21/7681
    • With the present invention, a plurality of contiguous openings within an integrated circuit are etched with high etch selectivity. The present invention includes the step of depositing a first masking layer adjacent a first opening layer. The first masking layer has a first pattern for defining a first opening in the first opening layer. The present invention also includes the step of depositing a second opening layer adjacent the first masking layer. Additionally, the present invention includes the step of depositing a second masking layer, that is comprised of a hard mask material, adjacent the second insulating layer. The second masking layer has a second pattern for defining a second opening in the second opening layer. The second pattern is aligned with the first pattern such that the first opening and the second opening are contiguous. With the second masking layer being comprised of a hard mask material, at least one of the first opening and the second opening is readily etched with an high selectivity etch process, such as a high temperature etch and/or a high polymer etch. With high etch selectivity, the present invention is especially amenable for small-geometry integrated circuit fabrication. Moreover, the present invention may be practiced to particular advantage during a dual damascene etch for a via hole and a trench line in integrated circuit metallization.
    • 利用本发明,以高蚀刻选择性蚀刻集成电路内的多个连续的开口。 本发明包括沉积与第一开口层相邻的第一掩蔽层的步骤。 第一掩模层具有用于限定第一开口层中的第一开口的第一图案。 本发明还包括沉积与第一掩蔽层相邻的第二开口层的步骤。 此外,本发明包括沉积与第二绝缘层相邻的由硬掩模材料构成的第二掩模层的步骤。 第二掩模层具有用于限定第二开口层中的第二开口的第二图案。 第二图案与第一图案对准,使得第一开口和第二开口是连续的。 在第二掩模层由硬掩模材料构成的情况下,第一开口和第二开口中的至少一个易于用高选择性蚀刻工艺(例如高温蚀刻和/或高聚合物蚀刻)蚀刻。 具有高蚀刻选择性,本发明特别适用于小几何集成电路制造。 此外,本发明可以在集成电路金属化中的通孔和沟槽线的双镶嵌蚀刻期间特别有利。