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61. 发明授权

US4727265A Semiconductor circuit having a current switch circuit which imparts a latch function to an input buffer for generating high amplitude signals 失效
标题翻译：具有电流开关电路的半导体电路，其向输入缓冲器提供锁存功能，用于产生高幅度信号
公开(公告)号：US4727265A
公开(公告)日：1988-02-23
申请号：US755910
申请日：1985-07-17
申请人： Hiroaki Nanbu , Noriyuki Honma , Kunihiko Yamaguchi , Kazuo Kanetani , Goro Kitsukawa
发明人： Hiroaki Nanbu , Noriyuki Honma , Kunihiko Yamaguchi , Kazuo Kanetani , Goro Kitsukawa
IPC分类号： G11C11/414 , G11C11/41 , H03K17/30 , H03K17/60 , H03K17/62 , H03K17/693 , H03K17/16 , H03K19/00 , H03K19/092 , H03L5/00
CPC分类号： H03K17/693 , H03K17/603 , H03K17/6292
摘要： A semiconductor circuit of a current mode type logic is provided having a reference voltage generating circuit which generates the reference voltage to be applied to the logic circuit in response to a clock signal to latch the state corresponding to an input signal at an instant of the clock signal input. The reference voltage has three levels in response to the voltage levels of the clock signal and the input signal: a middle voltage between the two high and low voltage levels of the input signal when the clock signal is at a first level voltage; a voltage higher than the high voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a high voltage; and a voltage lower than the low voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a second level voltage and the output signal is at a low voltage. This semiconductor circuit can relax restrictions on the signal amplitude due to the supply voltage and the saturation of the transistors, and, accordingly, allows processing signals having a much greater amplitude than was previously possible.
摘要翻译：提供电流模式型逻辑的半导体电路，其具有参考电压产生电路，该参考电压产生电路响应于时钟信号产生要施加到逻辑电路的参考电压，以在时钟瞬间锁存对应于输入信号的状态信号输入。参考电压响应于时钟信号和输入信号的电压电平而具有三个电平：当时钟信号处于第一电平电压时，输入信号的两个高电平和低电平电平之间的中间电压; 当所述时钟信号处于第二电平电压并且所述输出信号处于高电压时，所述电压高于所述输入信号的高电压电平; 以及当所述时钟信号处于第二电平电压并且所述输出信号处于第二电平电压且所述输出信号处于低电压时，所述电压低于所述输入信号的低电压电平。该半导体电路可以放宽由于晶体管的电源电压和饱和度导致的对信号幅度的限制，因此允许处理具有比之前可能的幅度大得多的信号。

62. 发明授权

US07400034B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07400034B2
公开(公告)日：2008-07-15
申请号：US11196267
申请日：2005-08-04
申请人： Kouichirou Noda , Shigenobu Kato , Goro Kitsukawa , Michihiro Mishima
发明人： Kouichirou Noda , Shigenobu Kato , Goro Kitsukawa , Michihiro Mishima
IPC分类号： H01L23/52
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C5/14 , G11C11/4097 , G11C2207/105 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/105 , H01L27/10897 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/45144 , H01L2224/48247 , H01L2224/49113 , H01L2224/49171 , H01L2224/49175 , H01L2924/01005 , H01L2924/01027 , H01L2924/01079 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： There is provided a large capacity memory such as a DRAM and an SDRAM n which bonding pads PS and PD are not located at the center, but are displaced from the center between memory array regions UL and UR, disposed on the upper side of a four-bank structure of banks 0 through 3, and memory array regions DL and DR, disposed on the lower side thereof. Secondly, the disposition of the bonding pads PS and PD is staggered on the right and left such that the right half bonding pads PD are shifted up relative to the left half bonding pads by about 30 μm. Only a sense amplifier, a column decoder and a main amplifier, which need to be near to the memory array regions DL and DR, are disposed between the bonding pads PS and PD, and the lower memory array regions DL and DR, and further indirect peripheral circuits are disposed on the upper side of the bonding pads PS and PD.
摘要翻译：提供了诸如DRAM和SDRAM n的大容量存储器，其中接合焊盘PS和PD不位于中心，而是位于设置在四个的上侧的存储器阵列区域UL和UR之间的中心存储体0至3的存储体结构以及位于其下侧的存储器阵列区域DL和DR。其次，接合焊盘PS和PD的布置在左右交错，使得右半边焊盘PD相对于左半键焊盘向上移动约30μm。需要靠近存储器阵列区域DL和DR的读出放大器，列解码器和主放大器设置在接合焊盘PS和PD以及下部存储器阵列区域DL和DR之间，并且进一步间接地外围电路设置在接合焊盘PS和PD的上侧。

63. 发明授权

US06970391B2 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions 失效
标题翻译：内置电源的半导体器件用于补偿工作条件和制造工艺条件的偏差
公开(公告)号：US06970391B2
公开(公告)日：2005-11-29
申请号：US10441207
申请日：2003-05-20
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12 , G11C8/00 , G11C8/10 , G11C11/4094 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944 , G11C7/04 , G11C7/02 , G11C11/34
CPC分类号： G11C7/12 , G11C5/14 , G11C5/147 , G11C8/10 , G11C11/4094 , G11C11/413 , H03K5/08 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K2217/0036
摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.
摘要翻译：半导体集成电路包括半导体芯片，设置在半导体芯片上用于接收来自外部电源的电压的电源端子，设置在半导体芯片上的内部电路，设置在半导体芯片上的电源电路，用于将从所述电源端子接收用于向所述内部电路提供由所述电压变换产生的源极电压的外部电源电压;以及控制电路，设置在所述半导体芯片上用于控制所述电源电路，其中，所述控制电路包括外部电源电压检测装置和/或温度检测装置，通过改变对内部电路的电源电压来响应来自外部电源电压检测装置和/或温度检测装置的信号，从而将内部电路的操作速度保持为不变。

64. 发明授权

US06740958B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06740958B2
公开(公告)日：2004-05-25
申请号：US10115101
申请日：2002-04-04
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L2900
CPC分类号： H01L27/0623 , H01L27/0214 , H01L27/0218 , H01L27/0922 , H01L27/105 , H01L27/10805
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

65. 发明授权

US6125075A Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions 失效
公开(公告)号：US6125075A
公开(公告)日：2000-09-26
申请号：US168998
申请日：1998-10-09
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12 , G11C8/00 , G11C8/10 , G11C11/4094 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944
CPC分类号： G11C7/12 , G11C11/4094 , G11C11/413 , G11C5/14 , G11C5/147 , G11C8/10 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K5/08 , H03K2217/0036
摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

66. 发明授权

US6067257A Semiconductor integrated circuit device having step-down voltage circuit 有权
标题翻译：具有降压电压电路的半导体集成电路器件
公开(公告)号：US6067257A
公开(公告)日：2000-05-23
申请号：US270677
申请日：1999-03-16
申请人： Goro Kitsukawa , Yoji Idei
发明人： Goro Kitsukawa , Yoji Idei
IPC分类号： G11C5/14 , G11C11/4074 , G11C7/00
CPC分类号： G11C5/147 , G11C11/4074
摘要： A semiconductor integrated circuit device is provided with an internal circuit which receives a source voltage supplied from an external terminal and is activated based on a voltage obtained by reducing the source voltage, and an output circuit which outputs a signal to be outputted produced by the internal circuit, through an external terminal in accordance with a timing signal. In the semiconductor integrated circuit device, a level shift circuit converts the signal produced by the internal circuit to a signal level corresponding to the level of the source voltage supplied from the external terminal. The output circuit outputs the level-shifted signal therefrom using a timing signal of a voltage level corresponding to the source voltage supplied from the external terminal.
摘要翻译：半导体集成电路器件具有内部电路，该内部电路接收从外部端子提供的源极电压，并且基于通过降低源极电压获得的电压而被激活;以及输出电路，其输出由内部产生的输出信号电路，通过外部端子根据定时信号。在半导体集成电路装置中，电平移位电路将由内部电路产生的信号转换为与从外部端子提供的源极电压的电平相对应的信号电平。输出电路使用与从外部端子提供的源极电压相对应的电压电平的定时信号输出电平移位信号。

67. 发明授权

US5644548A Dynamic random access memory having bipolar and C-MOS transistor 失效
标题翻译：具有双极和C-MOS晶体管的动态随机存取存储器
公开(公告)号：US5644548A
公开(公告)日：1997-07-01
申请号：US703521
申请日：1996-08-27
申请人： Goro Kitsukawa , Takao Watanabe , Ryoichi Hori , Noriyuki Honma , Kunihiko Yamaguchi , Kiyoo Ito , Masahiro Iwamura , Ikuro Masuda
发明人： Goro Kitsukawa , Takao Watanabe , Ryoichi Hori , Noriyuki Honma , Kunihiko Yamaguchi , Kiyoo Ito , Masahiro Iwamura , Ikuro Masuda
IPC分类号： G11C11/408 , G11C11/4091 , G11C11/4096 , G11C8/00
CPC分类号： G11C11/4087 , G11C11/4082 , G11C11/4091 , G11C11/4096
摘要： A dynamic random access memory device is provided having a dynamic memory cell, a word line coupled to the dynamic memory cell, a data line coupled to the dynamic memory cell, a precharge circuit coupled to the data line, a word driver coupled to the word line and a decoder coupled to the word driver. A plurality of address lines coupled to the decoder. The decoder has a first logic circuit whose inputs are connected to the plurality of address lines. The decoder also has a latch circuit whose input is connected to an output of the first logic circuit and whose output is connected to the word line.
摘要翻译：提供了一种动态随机存取存储器件，其具有动态存储器单元，耦合到动态存储单元的字线，耦合到动态存储单元的数据线，耦合到数据线的预充电电路，耦合到该字的字驱动器线和解码器耦合到字驱动器。耦合到解码器的多个地址线。解码器具有第一逻辑电路，其输入连接到多个地址线。解码器还具有一个锁存电路，其输入端连接到第一逻辑电路的输出，其输出端连接到字线。

68. 发明授权

US5587952A Dynamic random access memory including read preamplifiers activated before rewrite amplifiers 失效
标题翻译：动态随机存取存储器包括在重写放大器之前激活的读前置放大器
公开(公告)号：US5587952A
公开(公告)日：1996-12-24
申请号：US391537
申请日：1995-02-21
申请人： Goro Kitsukawa , Takao Watanabe , Ryoichi Hori , Noriyuki Honma , Kunihiko Yamaguchi , Kiyoo Itoh
发明人： Goro Kitsukawa , Takao Watanabe , Ryoichi Hori , Noriyuki Honma , Kunihiko Yamaguchi , Kiyoo Itoh
IPC分类号： G11C11/408 , G11C11/4091 , G11C11/4096 , G11C11/409 , G11C7/06
CPC分类号： G11C11/4087 , G11C11/4082 , G11C11/4091 , G11C11/4096
摘要： A dynamic random access memory is provided which includes word lines for accessing memory cells, data lines for transferring information from the memory cells, and rewrite amplifiers connected to the data lines for rewriting the information to corresponding memory cells. Read pre-amplifiers are also provided for sensing the information, together with common data lines for transferring output signals of the read pre-amplifiers. Each of the read pre-amplifiers has two insulated gate field-effect transistors, gates of which are connected to the data lines, and sources/drains of which are connected with the common data lines, such that the common data lines do not form current paths with the data lines. In addition, the read pre-amplifiers are activated before the rewrite amplifiers.
摘要翻译：提供了一种动态随机存取存储器，其包括用于访问存储单元的字线，用于从存储器单元传送信息的数据线，以及连接到数据线的重写放大器，用于将信息重写到相应的存储器单元。还提供读取前置放大器用于感测信息，以及公共数据线，用于传输读取的前置放大器的输出信号。每个读取的预放大器具有两个绝缘栅场效应晶体管，其栅极连接到数据线，并且其源极/漏极与公共数据线连接，使得公共数据线不形成电流路径与数据线。此外，读取的前置放大器在重写放大器之前被激活。

69. 发明授权

US5386135A Semiconductor CMOS memory device with separately biased wells 失效
标题翻译：半导体CMOS存储器件具有单独偏置的阱
公开(公告)号：US5386135A
公开(公告)日：1995-01-31
申请号：US229340
申请日：1994-04-12
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0623 , H01L27/0922 , H01L27/0218 , H01L27/105 , Y10S257/901 , Y10S257/904
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

70. 发明授权

US5377156A Semiconductor device incorporating main and stand-by boosted internal power supply for compensating for deviation on operating condition and fabrication process conditions 失效
标题翻译：采用主要和待机增强内部电源的半导体器件，用于补偿工作条件和制造工艺条件的偏差
公开(公告)号：US5377156A
公开(公告)日：1994-12-27
申请号：US985076
申请日：1992-12-03
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12 , G11C8/00 , G11C8/10 , G11C11/4094 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944
CPC分类号： G11C7/12 , G11C11/4094 , G11C11/413 , G11C5/14 , G11C5/147 , G11C8/10 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K5/08 , H03K2217/0036
摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.
摘要翻译：半导体集成电路包括半导体芯片，设置在半导体芯片上用于接收来自外部电源的电压的电源端子，设置在半导体芯片上的内部电路，设置在半导体芯片上的电源电路，用于将从所述电源端子接收用于向所述内部电路提供由所述电压变换产生的源极电压的外部电源电压;以及控制电路，设置在所述半导体芯片上用于控制所述电源电路，其中，所述控制电路包括外部电源电压检测装置和/或温度检测装置，通过改变对内部电路的电源电压来响应来自外部电源电压检测装置和/或温度检测装置的信号，从而将内部电路的操作速度保持为不变。

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