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1. 发明授权

US07400034B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07400034B2
公开(公告)日：2008-07-15
申请号：US11196267
申请日：2005-08-04
申请人： Kouichirou Noda , Shigenobu Kato , Goro Kitsukawa , Michihiro Mishima
发明人： Kouichirou Noda , Shigenobu Kato , Goro Kitsukawa , Michihiro Mishima
IPC分类号： H01L23/52
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C5/14 , G11C11/4097 , G11C2207/105 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/105 , H01L27/10897 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/45144 , H01L2224/48247 , H01L2224/49113 , H01L2224/49171 , H01L2224/49175 , H01L2924/01005 , H01L2924/01027 , H01L2924/01079 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： There is provided a large capacity memory such as a DRAM and an SDRAM n which bonding pads PS and PD are not located at the center, but are displaced from the center between memory array regions UL and UR, disposed on the upper side of a four-bank structure of banks 0 through 3, and memory array regions DL and DR, disposed on the lower side thereof. Secondly, the disposition of the bonding pads PS and PD is staggered on the right and left such that the right half bonding pads PD are shifted up relative to the left half bonding pads by about 30 μm. Only a sense amplifier, a column decoder and a main amplifier, which need to be near to the memory array regions DL and DR, are disposed between the bonding pads PS and PD, and the lower memory array regions DL and DR, and further indirect peripheral circuits are disposed on the upper side of the bonding pads PS and PD.
摘要翻译：提供了诸如DRAM和SDRAM n的大容量存储器，其中接合焊盘PS和PD不位于中心，而是位于设置在四个的上侧的存储器阵列区域UL和UR之间的中心存储体0至3的存储体结构以及位于其下侧的存储器阵列区域DL和DR。其次，接合焊盘PS和PD的布置在左右交错，使得右半边焊盘PD相对于左半键焊盘向上移动约30μm。需要靠近存储器阵列区域DL和DR的读出放大器，列解码器和主放大器设置在接合焊盘PS和PD以及下部存储器阵列区域DL和DR之间，并且进一步间接地外围电路设置在接合焊盘PS和PD的上侧。

2. 发明申请

US20050263811A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050263811A1
公开(公告)日：2005-12-01
申请号：US11196267
申请日：2005-08-04
申请人： Kouichirou Noda , Shigenobu Kato , Goro Kitsukawa , Michihiro Mishima
发明人： Kouichirou Noda , Shigenobu Kato , Goro Kitsukawa , Michihiro Mishima
IPC分类号： G11C11/407 , G11C5/02 , G11C11/401 , G11C11/4097 , H01L21/8242 , H01L23/50 , H01L27/02 , H01L27/10 , H01L27/105 , H01L27/108
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C5/14 , G11C11/4097 , G11C2207/105 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/105 , H01L27/10897 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/45144 , H01L2224/48247 , H01L2224/49113 , H01L2224/49171 , H01L2224/49175 , H01L2924/01005 , H01L2924/01027 , H01L2924/01079 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： There is provided a large capacity memory such as a DRAM and an SDRAM n which bonding pads PS and PD are not located at the center, but are displaced from the center between memeory array regions UL and UR, disposed on the upper side of a four-bank structure of banks 0 through 3, and memory array regions DL and DR, disposed on the lower side therof. Secondly, the disposition of the bonding pads PS and PD is staggered on the right and left such that the right half bonding pads PD are shifted up relative to the left half bonding pads by about 30 μm. Only a sense amplifier, a column decoder and a main amplifier, which need to be near to the memory array regions DL and DR, are disposed between the bonding pads PS and PD, and the lower memory array regions DL and DR, and further indirect peripheral circuits are disposed on the upper side of the bonding pads PS and PD.
摘要翻译：提供了诸如DRAM和SDRAM n的大容量存储器，其中接合焊盘PS和PD不位于中心，而是位于配置在四层的上侧的存储阵列区域UL和UR之间的中心存储体0至3的存储体结构以及位于下侧的存储器阵列区域DL和DR。其次，接合焊盘PS和PD的布置在左右交错，使得右半边焊盘PD相对于左半键焊盘向上移动约30μm。需要靠近存储器阵列区域DL和DR的读出放大器，列解码器和主放大器设置在接合焊盘PS和PD以及下部存储器阵列区域DL和DR之间，并且进一步间接地外围电路设置在接合焊盘PS和PD的上侧。

3. 发明申请

US20080265284A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080265284A1
公开(公告)日：2008-10-30
申请号：US12146654
申请日：2008-06-26
申请人： Kouichirou Noda , Shigenobu Kato , Goro Kitsukawa , Michihiro Mishima
发明人： Kouichirou Noda , Shigenobu Kato , Goro Kitsukawa , Michihiro Mishima
IPC分类号： H01L27/10 , H01L27/108
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C5/14 , G11C11/4097 , G11C2207/105 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/105 , H01L27/10897 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/45144 , H01L2224/48247 , H01L2224/49113 , H01L2224/49171 , H01L2224/49175 , H01L2924/01005 , H01L2924/01027 , H01L2924/01079 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device, formed on a semiconductor substrate, including a first memory array formed in a first region and including first word lines, first bit lines across the first word lines, and memory cells at intersections of the first word lines and the first bit lines, a second memory array which is formed in a second region and including second word lines, second bit lines across the second word lines, and memory cells at intersections of the second word lines and the second bit lines, and address pads located in a third region, in which the first region, the third region and the second region are arranged in that order in the first direction, the address input pads being arranged between a center axis of the first direction of the substrate and the first region, and no address input pads are arranged between the center axis and the second region.
摘要翻译：一种形成在半导体衬底上的半导体器件，包括形成在第一区域中并包括第一字线的第一存储器阵列，跨越第一字线的第一位线以及第一字线和第一位线的交叉处的存储器单元第二存储器阵列，其形成在第二区域中，并且包括第二字线，跨越第二字线的第二位线，以及在第二字线和第二位线的交点处的存储单元，以及位于第三字线区域，其中第一区域，第三区域和第二区域沿第一方向以该顺序排列，地址输入焊盘布置在基板的第一方向的中心轴线和第一区域之间，并且没有地址输入垫布置在中心轴线和第二区域之间。

4. 发明授权

US07638871B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07638871B2
公开(公告)日：2009-12-29
申请号：US12146654
申请日：2008-06-26
申请人： Kouichirou Noda , Shigenobu Kato , Goro Kitsukawa , Michihiro Mishima
发明人： Kouichirou Noda , Shigenobu Kato , Goro Kitsukawa , Michihiro Mishima
IPC分类号： H01L23/52
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C5/14 , G11C11/4097 , G11C2207/105 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/105 , H01L27/10897 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/45144 , H01L2224/48247 , H01L2224/49113 , H01L2224/49171 , H01L2224/49175 , H01L2924/01005 , H01L2924/01027 , H01L2924/01079 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device, formed on a semiconductor substrate, including a first memory array formed in a first region and including first word lines, first bit lines across the first word lines, and memory cells at intersections of the first word lines and the first bit lines, a second memory array which is formed in a second region and including second word lines, second bit lines across the second word lines, and memory cells at intersections of the second word lines and the second bit lines, and address pads located in a third region, in which the first region, the third region and the second region are arranged in that order in the first direction, the address input pads being arranged between a center axis of the first direction of the substrate and the first region, and no address input pads are arranged between the center axis and the second region.
摘要翻译：一种形成在半导体衬底上的半导体器件，包括形成在第一区域中并包括第一字线的第一存储器阵列，跨越第一字线的第一位线以及第一字线和第一位线的交叉处的存储器单元第二存储器阵列，其形成在第二区域中，并且包括第二字线，跨越第二字线的第二位线，以及在第二字线和第二位线的交点处的存储单元，以及位于第三字线区域，其中第一区域，第三区域和第二区域沿第一方向以该顺序排列，地址输入焊盘布置在基板的第一方向的中心轴线和第一区域之间，并且没有地址输入垫布置在中心轴线和第二区域之间。

5. 发明授权

US06504770B2 Semiconductor memory 有权
公开(公告)号：US06504770B2
公开(公告)日：2003-01-07
申请号：US10067231
申请日：2002-02-07
申请人： Goro Kitsukawa , Toshitsugu Ueda , Manabu Ishimatsu , Michihiro Mishima
发明人： Goro Kitsukawa , Toshitsugu Ueda , Manabu Ishimatsu , Michihiro Mishima
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/81 , G11C29/814 , H01L27/105 , H01L27/10897
摘要： There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.

6. 发明授权

US06191983B1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06191983B1
公开(公告)日：2001-02-20
申请号：US09445964
申请日：1999-12-16
申请人： Goro Kitsukawa , Toshitsugu Ueda , Manabu Ishimatsu , Michihiro Mishima
发明人： Goro Kitsukawa , Toshitsugu Ueda , Manabu Ishimatsu , Michihiro Mishima
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/81 , G11C29/814 , H01L27/105 , H01L27/10897
摘要： There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.
摘要翻译：提供了一种半导体存储器，其允许将冗余存储器单元布置在中心，同时保持直接外围电路的布局单元的连续性，并且允许提高存储单元和直接外围电路的总产量。本发明的半导体存储器是使用分层字线结构或多分割位线结构的64M位或256M位DRAM，并且包括主行解码器区域，主字驱动器区域，列解码器区域，外围电路/焊盘区域，存储单元阵列，读出放大器区域，子字驱动器区域，交叉区域等形成在一个半导体芯片上。

7. 发明授权

US06407952B1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06407952B1
公开(公告)日：2002-06-18
申请号：US09716252
申请日：2000-11-21
申请人： Goro Kitsukawa , Toshitsugu Ueda , Manabu Ishimatsu , Michihiro Mishima
发明人： Goro Kitsukawa , Toshitsugu Ueda , Manabu Ishimatsu , Michihiro Mishima
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/81 , G11C29/814 , H01L27/105 , H01L27/10897
摘要： There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.
摘要翻译：提供了一种半导体存储器，其允许将冗余存储器单元布置在中心，同时保持直接外围电路的布局单元的连续性，并且允许提高存储单元和直接外围电路的总产量。本发明的半导体存储器是使用分层字线结构或多分割位线结构的64M位或256M位DRAM，并且包括主行解码器区域，主字驱动器区域，列解码器区域，外围电路/焊盘区域，存储单元阵列，读出放大器区域，子字驱动器区域，交叉区域等形成在一个半导体芯片上。

8. 发明授权

US06891761B2 Semiconductor device and manufacturing method 失效
标题翻译：半导体器件及制造方法
公开(公告)号：US06891761B2
公开(公告)日：2005-05-10
申请号：US10767053
申请日：2004-01-30
申请人： Yukihiro Kumagai , Hideo Miura , Hiroyuki Ohta , Michihiro Mishima , Katsuyuki Nakanishi
发明人： Yukihiro Kumagai , Hideo Miura , Hiroyuki Ohta , Michihiro Mishima , Katsuyuki Nakanishi
IPC分类号： H01L21/76 , H01L21/8234 , H01L21/8242 , H01L27/08 , H01L27/108 , G11C16/06
CPC分类号： H01L29/7842 , H01L21/823412 , H01L21/823481 , H01L27/10873 , H01L27/10897
摘要： A semiconductor device is provided including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active area in which the transistor is formed). By such composition, stress growing in the active area due to the shallow trench isolation is equalized among the transistors, and, thereby, the characteristics of the transistors can be equalized.
摘要翻译：提供一种半导体器件，其包括使用期望具有相同特性的两个或更多个场效应晶体管的电路，能够实现高可靠性和优异的晶体管特性。期望具有相同特性的晶体管被放置在半导体器件中，以具有相同的STI沟槽宽度（与形成晶体管的有源区相邻的浅沟槽隔离的宽度）。通过这样的组成，由于浅沟槽隔离而在有源区中生长的应力在晶体管之间被均衡，从而可以使晶体管的特性相等。

9. 发明授权

US07371687B2 Electronic circuit device 失效
标题翻译：电子电路装置
公开(公告)号：US07371687B2
公开(公告)日：2008-05-13
申请号：US11475961
申请日：2006-06-28
申请人： Ryo Fujita , Osamu Kubo , Kouki Noguchi , Masaharu Kubo , Michihiro Mishima , Yasuhiko Takahashi
发明人： Ryo Fujita , Osamu Kubo , Kouki Noguchi , Masaharu Kubo , Michihiro Mishima , Yasuhiko Takahashi
IPC分类号： H01L23/52
CPC分类号： G06F11/261 , G06F11/267 , G06F15/7867 , H01L25/18 , H01L2224/16225 , H01L2924/00014 , H01L2924/09701 , H01L2924/13091 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.
摘要翻译：电子电路装置具有高密度安装板（2），微型计算机（3）和随机存取存储器（7）设置在其上，通过用于高速数据的专用存储器总线（12）彼此连接传输，由FPGA表示的可变逻辑电路的可编程器件（8）和可存储微型计算机的操作程序的电可重写非易失性存储器（16）。高密度安装板在底面上具有外部安装销，使其可以以与系统片上多芯片模块相同的方式安装在母板上。通过在可编程器件上设置预期的逻辑功能，可以模拟由电子电路器件实现的基于硬件的功能。通过将操作程序写入非易失性存储器，可以模拟要实现的基于软件的功能。因此，该设备便于系统开发初期的调试，配置原型系统，有助于整个系统开发，原型制作和大规模生产的时间缩短。

10. 发明申请

US20060244122A1 Electronic circuit device 失效
标题翻译：电子电路装置
公开(公告)号：US20060244122A1
公开(公告)日：2006-11-02
申请号：US11475936
申请日：2006-06-28
申请人： Ryo Fujita , Osamu Kubo , Kouki Noguchi , Masaharu Kubo , Michihiro Mishima , Yasuhiko Takahashi
发明人： Ryo Fujita , Osamu Kubo , Kouki Noguchi , Masaharu Kubo , Michihiro Mishima , Yasuhiko Takahashi
IPC分类号： H01L23/52
CPC分类号： G06F11/261 , G06F11/267 , G06F15/7867 , H01L25/18 , H01L2224/16225 , H01L2924/00014 , H01L2924/09701 , H01L2924/13091 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.
摘要翻译：电子电路装置具有高密度安装板（2），微型计算机（3）和随机存取存储器（7）设置在其上，通过用于高速数据的专用存储器总线（12）彼此连接传输，由FPGA表示的可变逻辑电路的可编程器件（8）和可存储微型计算机的操作程序的电可重写非易失性存储器（16）。高密度安装板在底面上具有外部安装销，使其可以以与系统片上多芯片模块相同的方式安装在母板上。通过在可编程器件上设置预期的逻辑功能，可以模拟由电子电路器件实现的基于硬件的功能。通过将操作程序写入非易失性存储器，可以模拟要实现的基于软件的功能。因此，该设备便于系统开发初期的调试，配置原型系统，有助于整个系统开发，原型制作和大规模生产的时间缩短。

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