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61. 发明授权

US07132851B2 Columnar floorplan 有权
公开(公告)号：US07132851B2
公开(公告)日：2006-11-07
申请号：US10618404
申请日：2003-07-11
申请人： Steven P. Young
发明人： Steven P. Young
IPC分类号： H03K19/177
CPC分类号： H01L27/11898 , H01L27/0207 , H01L27/11803 , H01L27/11807
摘要： An FPGA is laid out as a plurality of repeatable tiles, wherein the tiles are disposed in columns that extend from one side of the die to another side of the die, and wherein each column includes tiles primarily of one type. Because substantially all die area of a column is due to tiles of a single type, the width of the tiles of each column can be optimized and is largely independent of the size of the other types of tiles on the die. The confines of each type of tile can therefore be set to match the size of the circuitry of the tile. Rather than providing a ring of input/output blocks (IOBs) around the die periphery, IOB tiles are disposed in columns only. Where more than two columns worth of IOBs is required, more than two columns of IOB tiles can be provided.

62. 发明授权

US07095253B1 Programmable multi-chip module 有权
标题翻译：可编程多芯片模块
公开(公告)号：US07095253B1
公开(公告)日：2006-08-22
申请号：US10624832
申请日：2003-07-21
申请人： Steven P. Young
发明人： Steven P. Young
IPC分类号： H03K19/00
CPC分类号： H01L25/50 , H01L23/5382 , H01L23/5386 , H01L25/0652 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/15192 , H01L2224/05599
摘要： A multi-chip module comprising: a first IC having a first column of tiles, where each tile includes programmable logic; a second IC having a second column of tiles, where the second column is aligned with the first column; and a carrier die having signal lines, where a tile in the first column is directly connected to a tile in the second column via one of the signal lines.
摘要翻译：一种多芯片模块，包括：具有第一列瓦片的第一IC，其中每个瓦片包括可编程逻辑; 第二IC，具有第二列瓦，其中第二列与第一列对准; 以及具有信号线的载体裸片，其中第一列中的瓦片经由信号线之一直接连接到第二列中的瓦片。

63. 发明授权

US07089527B2 Structures and methods for selectively applying a well bias to portions of a programmable device 有权
公开(公告)号：US07089527B2
公开(公告)日：2006-08-08
申请号：US10853982
申请日：2004-05-25
申请人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
发明人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
IPC分类号： G06F17/50
CPC分类号： H03K19/17792 , G06F17/5054 , H01L27/0928 , H01L27/11807
摘要： Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

64. 发明授权

US07053654B1 PLD lookup table including transistors of more than one oxide thickness 有权
标题翻译： PLD查找表包括多于一个氧化物厚度的晶体管
公开(公告)号：US07053654B1
公开(公告)日：2006-05-30
申请号：US10869139
申请日：2004-06-15
申请人： Steven P. Young , Venu M. Kondapalli , Martin L. Voogel
发明人： Steven P. Young , Venu M. Kondapalli , Martin L. Voogel
IPC分类号： G06F7/38
CPC分类号： H03K19/1778 , H03K19/1737 , H03K19/17728
摘要： A structure that can be used, for example, to implement a lookup table for a programmable logic device (PLD). The structure includes configuration memory cells, pass transistors, and a buffer. The pass transistors pass the output of a selected configuration memory cell to the buffer, and are controlled by data input signals of the structure. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The memory cells and buffer include transistors having a second oxide thickness thinner than the first oxide thickness, and operate at a second operating voltage lower than the first operating voltage. The data input signals are provided at the first operating voltage. Some embodiments include data generating circuits that include transistors having the first oxide thickness. Gate lengths can also vary between the memory cell transistors, pass transistors, buffer transistors, and data generating circuits.
摘要翻译：可用于例如实现可编程逻辑器件（PLD）的查找表的结构。该结构包括配置存储单元，传输晶体管和缓冲器。传输晶体管将所选配置存储单元的输出传递到缓冲器，并由结构的数据输入信号控制。传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。存储单元和缓冲器包括具有比第一氧化物厚度薄的第二氧化物厚度的晶体管，并且在低于第一工作电压的第二工作电压下工作。在第一工作电压下提供数据输入信号。一些实施例包括包括具有第一氧化物厚度的晶体管的数据产生电路。栅极长度也可以在存储单元晶体管，传输晶体管，缓冲晶体管和数据产生电路之间变化。

65. 发明授权

US06768335B1 Integrated circuit multiplexer including transistors of more than one oxide thickness 有权
标题翻译：集成电路多路复用器包括多于一个氧化物厚度的晶体管
公开(公告)号：US06768335B1
公开(公告)日：2004-07-27
申请号：US10354520
申请日：2003-01-30
申请人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
发明人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
IPC分类号： G06F738
CPC分类号： H03K17/005 , H03K17/693 , H03K19/17736 , H03K19/1778
摘要： A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.
摘要翻译：可以用于例如可编程逻辑器件（PLD）中的多路复用器。多路复用器包括将多个输入值中选择的一个输入值传送到内部节点的多个传输晶体管，驱动提供多路复用器输出信号的缓冲器。可以例如通过存储在PLD的存储器单元中的值来控制传输晶体管。传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。缓冲器包括具有第二和较薄氧化物厚度的晶体管，并且在第二和较低工作电压下操作。在使用存储器单元来控制传输晶体管的情况下，存储单元包括具有第一氧化物厚度并在第一工作电压下工作的晶体管。一些实施例还包括用于每个传输晶体管，缓冲晶体管和存储单元晶体管的栅极长度变化的晶体管。

66. 发明授权

US06526557B1 Architecture and method for partially reconfiguring an FPGA 有权
标题翻译：部分重新配置FPGA的架构和方法
公开(公告)号：US06526557B1
公开(公告)日：2003-02-25
申请号：US09624818
申请日：2000-07-25
申请人： Steven P. Young , Trevor J. Bauer
发明人： Steven P. Young , Trevor J. Bauer
IPC分类号： G06F1750
CPC分类号： H03K19/17756
摘要： An FPGA architecture and method enables partial reconfiguration of selected configurable logic blocks (CLBs) connected to an address line without affecting other CLBs connected to the same address line. Partial reconfiguration at a memory cell resolution is achieved by manipulating the input voltages applied to the address and data lines of an FPGA so that certain memory cells are programmed while other memory cells are not programmed. In addition, partial reconfiguration at a CLB resolution can be achieved by hardwiring the FPGA to enable selection of individual CLBs for reconfiguration.
摘要翻译： FPGA架构和方法使得能够部分重新配置连接到地址线的所选择的可配置逻辑块（CLB），而不会影响连接到同一地址线的其他CLB。通过操纵施加到FPGA的地址和数据线的输入电压来实现存储器单元分辨率的部分重新配置，使得某些存储器单元被编程而其他存储器单元未被编程。此外，CLB分辨率的部分重新配置可以通过硬连线FPGA来实现，以便能够选择单个CLB进行重新配置。

67. 发明授权

US06445209B1 FPGA lookup table with NOR gate write decoder and high speed read decoder 有权
标题翻译：具有NOR门写解码器和高速读取解码器的FPGA查找表
公开(公告)号：US06445209B1
公开(公告)日：2002-09-03
申请号：US09566398
申请日：2000-05-05
申请人： Steven P. Young , Trevor J. Bauer , Richard A. Carberry
发明人： Steven P. Young , Trevor J. Bauer , Richard A. Carberry
IPC分类号： H03K19177
CPC分类号： H03K19/17728 , H03K19/1737
摘要： A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The write decoder includes NOR gates that generate select signals used to address individual memory circuits during write operations. For dynamic latching during reading or shifting, each memory circuit includes an inverter circuit connected between the memory cell and the output terminal of the memory circuit. The read decoder includes a multiplexing circuit made up of a series of 2-to-1 multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and a second LUT.
摘要翻译：用于可编程逻辑器件（PLD）的快速，节省空间的查找表（LUT），其中修改LUT的写解码器，读取解码器和存储器块以提供高性能，同时提供高效布局。写解码器和读取解码器都由LUT输入信号控制，数据信号被直接发送到存储器块的每个存储电路（即不经过写入解码器）。写入解码器包括NOR门，其产生用于在写入操作期间寻址各个存储器电路的选择信号。对于读取或移位期间的动态锁存，每个存储器电路包括连接在存储器单元和存储器电路的输出端之间的反相器电路。读取解码器包括由从PLD的互连资源接收的输入信号直接控制的一系列2对1复用器组成的复用电路。在一个实施例中，可配置逻辑块被提供有由第一LUT和第二LUT共享的单个写入解码器。

68. 发明授权

US06323681B1 Circuits and methods for operating a multiplexer array 有权
标题翻译：用于操作多路复用器阵列的电路和方法
公开(公告)号：US06323681B1
公开(公告)日：2001-11-27
申请号：US09546305
申请日：2000-04-10
申请人： Roman Iwanczuk , Steven P. Young , David P. Schultz
发明人： Roman Iwanczuk , Steven P. Young , David P. Schultz
IPC分类号： H01L2500
CPC分类号： H03K19/17776 , H03K19/17748 , H03K19/1776
摘要： An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer. Using the invention, a bit stream designed for an old device can be used for a new device having additional configuration memory cells.
摘要翻译： FPGA配置存储器被分成具有唯一地址的柱状帧。配置数据被加载到配置寄存器中，并且并行传送配置数据。在优选实施例中，输入寄存器，影子输入寄存器和多路复用器阵列允许使用比常规FPGA更大数量的输入位的有效配置数据传送。灵活的外部接口使得能够连接到从预定最大宽度到其选定分数的总线大小。通过使用影子寄存器以最小的延迟逐帧地将这样的数据驱动到存储器单元中，并且通过采用多路复用器阵列来利用更宽的配置数据传输总线，使配置数据传输更有效。通过采用支持双向数据传输的配置寄存器逻辑，配置回读的速度基本上等于输入配置数据的速率。使用本发明，为旧设备设计的比特流可以用于具有附加配置存储单元的新设备。

69. 发明授权

US06278290B1 Method and circuit for operating programmable logic devices during power-up and stand-by modes 有权
标题翻译：在上电和待机模式下操作可编程逻辑器件的方法和电路
公开(公告)号：US06278290B1
公开(公告)日：2001-08-21
申请号：US09374490
申请日：1999-08-13
申请人： Steven P. Young
发明人： Steven P. Young
IPC分类号： H01L2500
CPC分类号： H03K19/17772 , H03K19/17736 , H03K19/17764 , H03K19/1778 , H03K19/17784
摘要： A PLD includes buffered interconnect resources and configurable logic circuits that are controlled by data stored in a configuration memory. Each buffer of the buffered interconnect resources includes a feedback pull-up transistor. To avoid crowbar current problems, a high voltage is transmitted to the input terminals of all buffers before configuration, thereby biasing all buffers into a high feedback voltage mode. In one embodiment, the high voltage is transmitted to the buffers using a global control signal that forces all output drivers to generate high output voltages, and then turning on all pass transistors of the interconnect resources to broadcast the high voltages to every buffer. After configuration, the global control signal is de-activated. In another embodiment, each buffer circuit includes a second pull-up device that is turned on at power-up to force all buffers into the high feedback mode. In this embodiment, all pass transistors of the interconnect resources are turned off before configuration. In yet another embodiment, another global control signal is transmitted to all state devices of the PLD at the beginning of a stand-by/reconfiguration mode. In response to the additional control signal, all state devices ignore subsequent signals from the interconnect resources until configuration is completed and all output drivers are returned to their pre-stand-by operation state.
摘要翻译： PLD包括由存储在配置存储器中的数据控制的缓冲互连资源和可配置逻辑电路。缓冲互连资源的每个缓冲器包括反馈上拉晶体管。为了避免电涌现象出现问题，高电压在配置之前传输到所有缓冲器的输入端，从而将所有缓冲器偏置为高反馈电压模式。在一个实施例中，使用强制所有输出驱动器产生高输出电压的全局控制信号将高电压传输到缓冲器，然后接通互连资源的所有传输晶体管以将高电压广播到每个缓冲器。配置完成后，全局控制信号被禁用。在另一个实施例中，每个缓冲电路包括第二上拉装置，其在上电时导通，以迫使所有缓冲器进入高反馈模式。在本实施例中，互连资源的全部通过晶体管在配置之前被关闭。在另一个实施例中，在待机/重新配置模式开始时，另一个全局控制信号被发送到PLD的所有状态设备。响应于附加控制信号，所有状态设备忽略来自互连资源的后续信号，直到配置完成并且所有输出驱动器返回到其待机前操作状态。

70. 发明授权

US06204695B1 Clock-gating circuit for reducing power consumption 有权
标题翻译：时钟门控电路，用于降低功耗
公开(公告)号：US06204695B1
公开(公告)日：2001-03-20
申请号：US09336357
申请日：1999-06-18
申请人： Peter H. Alfke , Alvin Y. Ching , Scott O. Frake , Jennifer Wong , Steven P. Young
发明人： Peter H. Alfke , Alvin Y. Ching , Scott O. Frake , Jennifer Wong , Steven P. Young
IPC分类号： H03H19096
CPC分类号： G06F1/10
摘要： A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.
摘要翻译：为逻辑器件提供时钟选通电路，可降低器件资源需求，消除用户定义自己的时钟选通电路的需要，并消除不期望的时钟信号干扰，如毛刺和欠压脉冲。在一个实施例中，时钟选通电路包括用于接收输入时钟信号的输入端; 用于接收时钟使能信号的输入端; 存储锁存器，其耦合以接收所述输入时钟信号和所述时钟使能信号，并且作为响应，提供时钟门控制信号; 以及耦合以接收输入时钟信号和时钟门控制信号的逻辑门。逻辑门选择地响应于时钟门控制信号路由输入时钟信号，由此提供输出时钟信号。

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