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61. 发明授权

US06730591B2 Method of using silicon rich carbide as a barrier material for fluorinated materials 失效
标题翻译：使用富碳化碳作为氟化材料的阻挡材料的方法
公开(公告)号：US06730591B2
公开(公告)日：2004-05-04
申请号：US10186532
申请日：2002-07-01
申请人： Licheng Han , Xu Yi , Simon Chooi , Mei Sheng Zhou , Joseph Zhifeng Xie
发明人： Licheng Han , Xu Yi , Simon Chooi , Mei Sheng Zhou , Joseph Zhifeng Xie
IPC分类号： H01L214763
CPC分类号： H01L21/76834 , H01L21/02167 , H01L21/02211 , H01L21/02274 , H01L21/3127 , H01L21/314 , H01L21/31629 , H01L21/76801 , H01L21/76807 , H01L21/76831 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.
摘要翻译：一种在半导体器件中形成互连结构的方法，包括以下步骤。提供半导体结构。在第一实施例中，在半导体结构上形成至少一条金属线。在金属线和半导体结构之上形成富含碳的碳化物阻挡层。最后，在富含硅的碳化物层上形成可被氟化的介电层。在第二实施例中，在半导体结构上形成至少一个可被氟化的氟化介电层。图案化电介质层以在其中形成开口。在开口内形成富含碳的碳化物阻挡层。在结构上沉积金属化层，填充富含硅的碳化物阻挡层衬里的开口。最后，金属化层可以被平坦化以在富含硅的碳化物阻挡层衬里的开口内形成平坦化的金属结构。

62. 发明授权

US06524963B1 Method to improve etching of organic-based, low dielectric constant materials 失效
标题翻译：改善有机系低介电常数材料蚀刻的方法
公开(公告)号：US06524963B1
公开(公告)日：2003-02-25
申请号：US09421510
申请日：1999-10-20
申请人： Mei Sheng Zhou , Simon Chooi , Jian Xun Li
发明人： Mei Sheng Zhou , Simon Chooi , Jian Xun Li
IPC分类号： H01L21302
CPC分类号： H01L21/31116 , H01L21/02118 , H01L21/0212 , H01L21/0217 , H01L21/022 , H01L21/02203 , H01L21/02271 , H01L21/31138 , H01L21/312 , H01L21/76802
摘要： A method etching an organic-based, low dielectric constant material in the manufacture of an integrated circuit device has been achieved. Organic materials without silicon and organic materials without fluorine can be etched by using, for example, hydrazine or ammonia gas. Organic materials with silicon can also be etched with the addition of a fluorine-containing or chlorine-containing gas. A semiconductor substrate is provided. A low dielectric constant organic-based material is deposited overlying the semiconductor substrate. The low dielectric constant organic-based material is etched to form desirable features using a plasma containing a gas comprising a nitrogen and hydrogen containing molecule, and the integrated circuit device is completed.
摘要翻译：已经实现了在制造集成电路器件中蚀刻有机基低介电常数材料的方法。不含硅的有机材料和无氟的有机材料可以通过使用例如肼或氨气进行蚀刻。也可以通过添加含氟或含氯气体来蚀刻具有硅的有机材料。提供半导体衬底。沉积在半导体衬底上的低介电常数有机基材料。使用包含含有氮和氢的分子的气体的等离子体来蚀刻低介电常数有机基材料以形成期望的特征，并且完成集成电路器件。

63. 发明授权

US06513374B2 Apparatus to quantify the adhesion of film 失效
公开(公告)号：US06513374B2
公开(公告)日：2003-02-04
申请号：US09771512
申请日：2001-01-29
申请人： Loh-Nah Luona Goh , Siew-Lok Toh , Simon Chooi , Tong-Earn Tay
发明人： Loh-Nah Luona Goh , Siew-Lok Toh , Simon Chooi , Tong-Earn Tay
IPC分类号： G01F1700
CPC分类号： H01L21/67132 , G01N19/04
摘要： A new apparatus is provided for the quantification of the adhesion of a film over a substrate. In particular, the peeling force and the rate of peeling are quantified by providing a first means for measuring the peeling force, a second means for measuring the rate of peeling, a third means for securing a piece of wafer, an adhesive tape, a tape holder and a resilient, flexible component.

64. 发明授权

US06376353B1 Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects 有权
标题翻译：用于铜镶嵌互连的铝和铜双金属焊盘方案
公开(公告)号：US06376353B1
公开(公告)日：2002-04-23
申请号：US09609167
申请日：2000-07-03
申请人： Mei Sheng Zhou , Sangki Hong , Simon Chooi
发明人： Mei Sheng Zhou , Sangki Hong , Simon Chooi
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/32134 , H01L21/76807 , H01L21/7684 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05096 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05546 , H01L2224/05624 , H01L2224/05647 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48699 , H01L2224/48724 , H01L2224/48747 , H01L2224/48847 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2224/48824 , H01L2924/00 , H01L2924/00015 , H01L2924/013 , H01L2924/00013
摘要： Improved processes for fabricating wire bond pads on pure copper damascene are disclosed by this invention. The invention relates to various methods of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of Al—Cu alloy top pad metal layers are described, which improve adhesion among the wire bond, top Al—Cu and the underlying copper pad metallurgy. This invention describes processes wherein a special Al—Cu bond layer or region is placed on top of the underlying copper pad metal. This Al—Cu bond pad on pure copper (with barrier layer in-between) provides for improved wire bond adhesion to the bond pad and prevents peeling during wire bond adhesion tests.
摘要翻译：本发明公开了用于在纯铜镶嵌件上制造引线接合焊盘的改进方法。本发明涉及用于半导体集成电路器件的各种制造方法，更具体地涉及形成Al-Cu合金顶部焊盘金属层，其改善了引线接合，顶部Al-Cu和下面的铜焊盘之间的粘附冶金。本发明描述了其中特殊的Al-Cu键合层或区域放置在下面的铜垫金属的顶部上的工艺。纯铜上的这种Al-Cu键合焊盘（其间具有阻挡层）提供了改善的与焊盘焊接粘合的线粘合，并且防止了焊线粘附试验期间的剥离。

65. 发明授权

US06271115B1 Post metal etch photoresist strip method 失效
标题翻译：后金属蚀刻光刻胶剥离法
公开(公告)号：US06271115B1
公开(公告)日：2001-08-07
申请号：US09604065
申请日：2000-06-26
申请人： Wen Jun Liu , Simon Chooi , Mei Sheng Zhou , Raymond Joy
发明人： Wen Jun Liu , Simon Chooi , Mei Sheng Zhou , Raymond Joy
IPC分类号： H01L214763
CPC分类号： H01L21/02071
摘要： An improved method for removing a photoresist mask from an etched aluminum pattern after etching the pattern in a chlorine containing plasma has been developed. The method is a five step process, in which the first step is in a microwave generated plasma containing O2 and H2O; the second step is in a microwave generated plasma containing O2 and N2; the third step is in a microwave generated plasma containing H2O; the fourth step is in a microwave generated plasma containing O2 and N2; and the fifth step is in a microwave generated plasma containing H2O. The first step which initiates removal of photoresist while simultaneously beginning the passivation process causes residue-free removal of photoresist following etching of aluminum or aluminum-copper layers in chlorine bearing etchants.
摘要翻译：已经开发了一种用于在含氯等离子体中蚀刻图案之后从蚀刻铝图案去除光致抗蚀剂掩模的改进方法。该方法是五步法，其中第一步是在微波产生的含有O 2和H 2 O的等离子体中; 第二步是在微波产生的含有O2和N2的等离子体中; 第三步是在微波产生的含有H 2 O的等离子体中; 第四步是在微波产生的含有O2和N2的等离子体中; 并且第五步是在含有H 2 O的微波产生的等离子体中。在同时开始钝化过程的同时开始除去光致抗蚀剂的第一步骤在蚀刻含氯蚀刻剂中的铝或铝 - 铜层之后会导致残留物去除光致抗蚀剂。

66. 发明授权

US06261942B1 Dual metal-oxide layer as air bridge 有权
标题翻译：双金属氧化物层作为气桥
公开(公告)号：US06261942B1
公开(公告)日：2001-07-17
申请号：US09490156
申请日：2000-01-24
申请人： Mei Sheng Zhou , Simon Chooi , Xu Yi
发明人： Mei Sheng Zhou , Simon Chooi , Xu Yi
IPC分类号： H01L214763
CPC分类号： H01L21/7682 , H01L21/312 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method for introducing air into the gaps between neighboring conducting structures in a microelectronics fabrication in order to reduce the capacitative coupling between them. A patterned metal layer is deposited on a substrate. The layer is lined with a CVD-oxide. A disposable gap-filling material is deposited over the lined metal layer. A two layer “air-bridge” is formed over the gap-fill by depositing a layer of TiN over a layer of CVD-oxide. This structure is rendered porous by several chemical processes. An oxygen plasma is passed through the porous air-bridge to react with and dissolve the gap-fill beneath it. The reaction products escape through the porous air-bridge resulting in air-filled gaps.
摘要翻译：一种在微电子制造中将空气引入相邻导电结构之间的间隙中以减少它们之间的电容耦合的方法。图案化的金属层沉积在基底上。该层衬有CVD氧化物。一次性间隙填充材料沉积在衬里的金属层上。通过在CVD氧化物层上沉积TiN层，在间隙填充上形成两层“空气桥”。这种结构通过几种化学方法使其多孔化。氧气等离子体通过多孔空气桥与其下方的间隙填充反应并溶解。反应产物通过多孔气桥逸出，导致空气填充的间隙。

67. 发明授权

US5948701A Self-aligned contact (SAC) etching using polymer-building chemistry 失效
标题翻译：使用聚合物构建化学的自对准接触（SAC）蚀刻
公开(公告)号：US5948701A
公开(公告)日：1999-09-07
申请号：US902846
申请日：1997-07-30
申请人： Simon Chooi , Mei-Sheng Zhou , Jian Xun Li
发明人： Simon Chooi , Mei-Sheng Zhou , Jian Xun Li
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L21/3065
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802 , H01L21/76804
摘要： A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a pair of microelectronic structures. There is then formed sequentially upon the substrate including the pair of microelectronic structures a first conformal dielectric layer followed by a second conformal dielectric layer followed by a third dielectric layer, where the second conformal dielectric layer serves as an etch stop layer with respect to the third dielectric layer in a first plasma etch method employed in forming in part a via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer at a location between the pair of microelectronic structures. The first plasma etch method employs an etchant gas composition which forms a passivating fluorocarbon polymer layer upon non-horizontal portions of the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer. There is then formed upon the third dielectric layer a patterned photoresist layer which defines the location between the pair of structures to be formed the via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer. There is then etched through the first plasma etch method the third dielectric layer and the second conformal dielectric layer to form a partial via while forming the passivating fluorocarbon polymer layer upon non-horizontal portions of the third dielectric layer, the second conformal dielectric layer and the first dielectric layer. Finally, there is then etched through a second plasma etch method the first conformal dielectric layer to form the via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer.
摘要翻译：在微电子学制造中通过介电层形成通孔的方法。首先提供了在微电子制造中使用的衬底。然后在衬底上形成一对微电子结构。然后在包括一对微电子结构的基板上依次形成第一共形介电层，随后是第二共形介电层，随后是第三介电层，其中第二共形绝缘层用作相对于第三绝缘层的蚀刻停止层在第一等离子体蚀刻方法中使用的介电层，其用于在所述一对微电子结构之间的位置处部分地通过所述第三介电层，所述第二共形介电层和所述第一共形介电层形成通孔。第一等离子体蚀刻方法采用蚀刻剂气体组合物，其在第三介电层，第二共形介电层和第一共形介电层的非水平部分上形成钝化氟碳聚合物层。然后在第三电介质层上形成图案化的光致抗蚀剂层，该图案化的光致抗蚀剂层限定通过第三介电层，第二共形介电层和第一共形介电层形成通孔的一对结构之间的位置。然后通过第一等离子体蚀刻方法蚀刻第三介电层和第二共形介电层以形成部分通孔，同时在第三介电层，第二共形介电层和第二保形介电层的非水平部分上形成钝化氟碳聚合物层第一电介质层。最后，然后通过第二等离子体蚀刻方法蚀刻第一共形介电层，以通过第三介电层，第二共形介电层和第一共形介电层形成通孔。

68. 发明授权

US07268048B2 Methods for elimination of arsenic based defects in semiconductor devices with isolation regions 有权
标题翻译：在具有隔离区域的半导体器件中消除基于砷的缺陷的方法
公开(公告)号：US07268048B2
公开(公告)日：2007-09-11
申请号：US10913214
申请日：2004-08-06
申请人： Yin-Min Felicia Goh , Simon Chooi , Teck Wee Lim , Vincent Sih , Chian Yuh Sin , Ping Yu Ee , Zainab Ismail , Cher Sian Chua
发明人： Yin-Min Felicia Goh , Simon Chooi , Teck Wee Lim , Vincent Sih , Chian Yuh Sin , Ping Yu Ee , Zainab Ismail , Cher Sian Chua
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/302
CPC分类号： H01L21/02057 , H01L21/02068 , H01L21/28518 , H01L21/76237 , H01L21/823814 , H01L21/823878 , H01L29/665 , H01L29/7833
摘要： Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a metal component of subsequently formed metal silicide regions. Arsenic ions implanted for N type source/drain regions are also implanted into insulator regions such as insulator filled shallow trench isolation regions. A hydrofluoric acid cycle used as a component of the pre-silicidation preparation procedure can release arsenic from the shallow trench isolation regions in the form of arsenic based defects, which in turn can re-deposit on the surface of source/drain region. Therefore pre-silicidation preparation treatments described in this invention feature removal of both native oxide and arsenic based defects from conductive surfaces prior to metal silicide formation. Methods include wet etch procedures featuring hydrofluoric acid and hydrogen peroxide, as well as spin dry and dry etch procedures both employed post hydrofluoric acid treatment to remove re-deposited arsenic based defects.
摘要翻译：已经开发了制备用于硅化程序的源极/漏极区域的导电区域的方法。该方法在沉积随后形成的金属硅化物区域的金属组分之前，特征在于去除自然氧化物以及从导电表面去除沉积的基于砷的缺陷。注入用于N型源极/漏极区域的砷离子也被注入绝缘体区域，例如绝缘体填充的浅沟槽隔离区域。用作预硅化物制备方法的组分的氢氟酸循环可以以基于砷的缺陷的形式从浅沟槽隔离区释放砷，其又可以沉积在源极/漏极区的表面上。因此，本发明中描述的预硅化制备处理在金属硅化物形成之前特征是从导电表面除去天然氧化物和砷的缺陷。方法包括以氢氟酸和过氧化氢为特征的湿法蚀刻程序，以及在氢氟酸处理之后采用的旋转干燥和干蚀刻方法，以去除重新沉积的基于砷的缺陷。

69. 发明授权

US06835989B2 Methods to form dual metal gates by incorporating metals and their conductive oxides 失效
标题翻译：通过引入金属及其导电氧化物形成双金属栅极的方法
公开(公告)号：US06835989B2
公开(公告)日：2004-12-28
申请号：US10736943
申请日：2003-12-16
申请人： Wenhe Lin , Mei-Sheng Zhou , Kin Leong Pey , Simon Chooi
发明人： Wenhe Lin , Mei-Sheng Zhou , Kin Leong Pey , Simon Chooi
IPC分类号： H01L2976
CPC分类号： H01L21/823842 , H01L29/66545
摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are oxygen implanted and oxidized. The PMOS gate has the higher work function.
摘要翻译：描述形成双金属栅极CMOS晶体管的方法。半导体衬底的NMOS和PMOS有源区由隔离区隔开。金属层沉积在每个有源区域中的栅极电介质层上。将氧离子注入到一个活性区域中的金属层中，以形成被氧化形成金属氧化物层的注入金属层。此后，金属层和金属氧化物层被图案化以在一个有源区域中形成金属栅极，而在另一个有源区域中形成金属氧化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。或者，两个栅极可以是金属氧化物栅极，其中两个栅极的氧化物浓度不同。或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。介电层被平坦化，从而暴露虚拟栅极。去除虚拟栅极留下栅极开口到半导体衬底。金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。一个或两个栅极是氧注入和氧化的。 PMOS栅极具有较高的功函数。

70. 发明授权

US06638365B2 Method for obtaining clean silicon surfaces for semiconductor manufacturing 有权
标题翻译：用于获得半导体制造的清洁硅表面的方法
公开(公告)号：US06638365B2
公开(公告)日：2003-10-28
申请号：US09972504
申请日：2001-10-09
申请人： Jianhui Ye , Simon Chooi , Alex See
发明人： Jianhui Ye , Simon Chooi , Alex See
IPC分类号： B08B300
CPC分类号： H01L21/02052 , C11D7/08 , C11D7/10 , C11D11/0047 , Y10S134/902
摘要： A method of preparing a silicon surface for a subsequent processing said such as thermal oxidation, or metal silicide formation, via use of a novel wet chemical clean procedure, has been developed. The novel wet chemical clean procedure is comprised of three specific stages, with the first stage featuring the removal of organic contaminants and the growth of a native oxide layer on the silicon surface. A second stage features removal of the native oxide layer and removal of metallic contaminants from the silicon surface, while the third stage is used to dry the silicon surface. The novel wet chemical clean procedure is performed in less time, and using less chemicals, then counterpart wet chemical cleans also used for the preparation of silicon surfaces for subsequent processing steps.
摘要翻译：已经开发了通过使用新的湿化学清洁程序来制备用于后续处理的硅表面的方法，例如热氧化或金属硅化物形成。新型湿化学清洁程序由三个特定阶段组成，第一阶段的特征在于去除有机污染物和硅表面上的自然氧化物层的生长。第二阶段特征在于去除天然氧化物层并从硅表面去除金属污染物，而第三阶段用于干燥硅表面。新的湿化学清洁程序在较短的时间内进行，使用较少的化学品，然后对应的湿化学清洗也用于制备硅表面用于后续处理步骤。

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