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1. 发明授权

US06566260B2 Non-metallic barrier formations for copper damascene type interconnects 有权
公开(公告)号：US06566260B2
公开(公告)日：2003-05-20
申请号：US09925822
申请日：2001-08-10
申请人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
发明人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
IPC分类号： H01L2144
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76831
摘要： A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

2. 发明授权

US06284657B1 Non-metallic barrier formation for copper damascene type interconnects 有权
标题翻译：铜镶嵌型互连的非金属阻挡层形成
公开(公告)号：US06284657B1
公开(公告)日：2001-09-04
申请号：US09512379
申请日：2000-02-25
申请人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
发明人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
IPC分类号： H01L2144
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76831
摘要： A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.
摘要翻译：用于形成具有非金属屏障的双镶嵌型导电互连的方法，其保护所述互连免受氟周围的低k，氟化介电材料的氟扩散。该方法的一个实施例特别适用于在0.15微米级的微电子制造中形成这种互连。

3. 发明授权

US06429122B2 Non metallic barrier formations for copper damascene type interconnects 失效
公开(公告)号：US06429122B2
公开(公告)日：2002-08-06
申请号：US09925820
申请日：2001-08-10
申请人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
发明人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76831
摘要： A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

4. 发明授权

US06352917B1 Reversed damascene process for multiple level metal interconnects 有权
标题翻译：用于多级金属互连的反向镶嵌工艺
公开(公告)号：US06352917B1
公开(公告)日：2002-03-05
申请号：US09598691
申请日：2000-06-21
申请人： Subhash Gupta , Mei-Sheng Zhou , Simon Chooi , Sangki Hong
发明人： Subhash Gupta , Mei-Sheng Zhou , Simon Chooi , Sangki Hong
IPC分类号： H01L214763
CPC分类号： H01L21/76885 , H01L21/76801 , H01L21/76802 , H01L21/76831 , H01L21/76834 , H01L21/76883 , H01L21/76897 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A new method of forming metal interconnect levels containing damascene interconnects and via plugs in the manufacture of an integrated circuit device has been achieved. The method creates a reversed dual damascene structure. A first dielectric layer is provided overlying a semiconductor substrate. The dielectric layer is patterned to form trenches for planned damascene interconnects. Insulating spacers may optionally be formed on the trench sidewalls. A conductive barrier layer is deposited overlying the dielectric layer and lining the trenches. A metal layer, preferably comprising copper, is deposited overlying the conductive barrier layer and filling the trenches. The metal layer and the conductive barrier layer are polished down to thereby form the damascene interconnects. A passivation layer may optionally be deposited. The damascene interconnects are patterned to form via plugs overlying the damascene interconnects. The patterning comprises partially etching down the damascene interconnects using a via mask overlying and protecting portions of the damascene interconnects. A trench mask also overlies and protects the first dielectric layer from metal contamination during the etching down.
摘要翻译：已经实现了在集成电路器件的制造中形成包含镶嵌互连和通孔插塞的金属互连级别的新方法。该方法创建一个反向的双镶嵌结构。第一电介质层设置在半导体衬底上。图案化电介质层以形成用于计划的大马士革互连的沟槽。可以可选地在沟槽侧壁上形成绝缘间隔物。导电阻挡层沉积在电介质层上并衬在沟槽上。沉积优选包含铜的金属层，覆盖在导电阻挡层上并填充沟槽。金属层和导电阻挡层被抛光，从而形成镶嵌互连。可以任选地沉积钝化层。大马士革互连被图案化以形成覆盖大马士革互连的通孔塞。图案化包括使用覆盖并保护大马士革互连部分的通孔掩模部分地蚀刻镶嵌互连。在蚀刻过程中，沟槽掩模也覆盖并保护第一介电层免受金属污染。

5. 发明授权

US06225202B1 Selective etching of unreacted nickel after salicidation 有权
标题翻译：腐蚀后对未反应的镍进行选择性蚀刻
公开(公告)号：US06225202B1
公开(公告)日：2001-05-01
申请号：US09598689
申请日：2000-06-21
申请人： Subhash Gupta , Mei-Sheng Zhou , Simon Chooi , Sangki Hong
发明人： Subhash Gupta , Mei-Sheng Zhou , Simon Chooi , Sangki Hong
IPC分类号： H01L214763
CPC分类号： H01L29/665 , C23F4/00 , H01L21/32136
摘要： A method for removing unreacted nickel or cobalt after silicidation using carbon monoxide dry stripping is described. Shallow trench isolation regions are formed in a semiconductor substrate surrounding and electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A nickel or cobalt layer is deposited over the gate electrode and associated source and drain regions, shallow trench isolation regions, and dielectric spacers. The semiconductor substrate is annealed whereby the nickel or cobalt layer overlying the gate electrode and said source and drain regions is transformed into a nickel or cobalt silicide layer and wherein the nickel or cobalt layer overlying the dielectric spacers and the shallow trench isolation regions is unreacted. The unreacted nickel or cobalt layer is exposed to a plasma containing carbon monoxide gas wherein the carbon monoxide gas reacts with the unreacted nickel or cobalt thereby removing the unreacted nickel or cobalt from the substrate to complete salicidation of the integrated circuit device.
摘要翻译：描述了使用一氧化碳干燥汽提在硅化后除去未反应的镍或钴的方法。在半导体衬底中形成浅沟槽隔离区域，该半导体衬底围绕并使活性区域与其它有源区域电隔离。在有源区域中形成栅电极和相关源极和漏极区，其中在栅电极的侧壁上形成有电介质间隔物。在栅极电极和相关的源极和漏极区域，浅沟槽隔离区域和介电间隔物上沉积镍或钴层。半导体衬底被退火，由此将覆盖在栅电极和所述源极和漏极区域上的镍或钴层转变成镍或钴硅化物层，并且其中覆盖电介质间隔物和浅沟槽隔离区的镍或钴层是未反应的。将未反应的镍或钴层暴露于含有一氧化碳气体的等离子体中，其中一氧化碳气体与未反应的镍或钴反应，从而从基板除去未反应的镍或钴，以完成集成电路器件的水化。

6. 发明授权

US06531390B2 Non-metallic barrier formations for copper damascene type interconnects 有权
公开(公告)号：US06531390B2
公开(公告)日：2003-03-11
申请号：US09925819
申请日：2001-08-10
申请人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
发明人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
IPC分类号： H01L218222
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76831
摘要： A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

7. 发明授权

US06489233B2 Non-metallic barrier formations for copper damascene type interconnects 有权
标题翻译：铜镶嵌型互连的非金属阻挡层
公开(公告)号：US06489233B2
公开(公告)日：2002-12-03
申请号：US09925821
申请日：2001-08-10
申请人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
发明人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76831
摘要： A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.
摘要翻译：用于形成具有非金属屏障的双镶嵌型导电互连的方法，其保护所述互连免受氟周围的低k，氟化介电材料的氟扩散。该方法的一个实施例特别适用于在0.15微米级的微电子制造中形成这种互连。

8. 发明授权

US06376353B1 Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects 有权
标题翻译：用于铜镶嵌互连的铝和铜双金属焊盘方案
公开(公告)号：US06376353B1
公开(公告)日：2002-04-23
申请号：US09609167
申请日：2000-07-03
申请人： Mei Sheng Zhou , Sangki Hong , Simon Chooi
发明人： Mei Sheng Zhou , Sangki Hong , Simon Chooi
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/32134 , H01L21/76807 , H01L21/7684 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05096 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05546 , H01L2224/05624 , H01L2224/05647 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48699 , H01L2224/48724 , H01L2224/48747 , H01L2224/48847 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2224/48824 , H01L2924/00 , H01L2924/00015 , H01L2924/013 , H01L2924/00013
摘要： Improved processes for fabricating wire bond pads on pure copper damascene are disclosed by this invention. The invention relates to various methods of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of Al—Cu alloy top pad metal layers are described, which improve adhesion among the wire bond, top Al—Cu and the underlying copper pad metallurgy. This invention describes processes wherein a special Al—Cu bond layer or region is placed on top of the underlying copper pad metal. This Al—Cu bond pad on pure copper (with barrier layer in-between) provides for improved wire bond adhesion to the bond pad and prevents peeling during wire bond adhesion tests.
摘要翻译：本发明公开了用于在纯铜镶嵌件上制造引线接合焊盘的改进方法。本发明涉及用于半导体集成电路器件的各种制造方法，更具体地涉及形成Al-Cu合金顶部焊盘金属层，其改善了引线接合，顶部Al-Cu和下面的铜焊盘之间的粘附冶金。本发明描述了其中特殊的Al-Cu键合层或区域放置在下面的铜垫金属的顶部上的工艺。纯铜上的这种Al-Cu键合焊盘（其间具有阻挡层）提供了改善的与焊盘焊接粘合的线粘合，并且防止了焊线粘附试验期间的剥离。

9. 发明授权

US06372636B1 Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene 有权
标题翻译：复合硅 - 金属氮化物屏障，以防铜铜镶嵌中金属氟化物的形成
公开(公告)号：US06372636B1
公开(公告)日：2002-04-16
申请号：US09587467
申请日：2000-06-05
申请人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
发明人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
IPC分类号： H01L214763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L21/76855
摘要： A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure -single, dual, or multi-structure- is disclosed in order to prevent the formation of fluorides in copper. In a first embodiment, the interconnection between the copper damascene and an underlying copper metal layer is made by forming an opening from the dual damascene structure to the underlying copper layer after the formation of the metal nitride layer over the amorphous silicon spacers formed on the inside walls of the dual damascene structure. In the second embodiment, the interconnection between the dual damascene structure and the underlying copper line is made from the dual damascene structure by etching into the underlying copper layer after the forming of the amorphous silicon spacers and before the forming of the metal nitride layer. In the third embodiment, the ternary metal silicon nitride spacer is formed by etching after having first formed the amorphous silicon layer and the nitride layer, in that order, and then etching the passivation/barrier layer at the bottom of the damascene structure into the underlying copper layer. In all three embodiments, metal nitride reacts with amorphous silicon to form a ternary metal silicon nitride having an excellent property of adhering to copper while at the same time for forming an excellent barrier to diffusion of copper.
摘要翻译：公开了一种形成非晶硅间隔物的方法，随后在铜镶嵌结构 - 单，双或多结构中在间隔物上形成金属氮化物，以防止在铜中形成氟化物。在第一实施例中，通过在形成在内部的非晶硅间隔物上形成金属氮化物层之后，通过从双镶嵌结构形成开口到下面的铜层来形成铜镶嵌层和下面的铜金属层之间的互连双镶嵌结构的墙壁。在第二实施例中，通过在形成非晶硅间隔物之后并且在形成金属氮化物层之前通过蚀刻到下面的铜层中，由双镶嵌结构制造双镶嵌结构和下面的铜线之间的互连。在第三实施例中，三元金属氮化硅间隔物依次先形成非晶硅层和氮化物层后，通过蚀刻形成，然后在镶嵌结构的底部蚀刻钝化/阻挡层，形成底层铜层。在所有三个实施例中，金属氮化物与非晶硅反应形成具有优异的粘附铜特性的三元金属氮化硅，同时形成对铜的扩散的优异屏障。

10. 发明申请

US20110117701A1 Fiducial Scheme Adapted for Stacked Integrated Circuits 有权
标题翻译：适应堆叠集成电路的基准方案
公开(公告)号：US20110117701A1
公开(公告)日：2011-05-19
申请号：US13004642
申请日：2011-01-11
申请人： Robert Patti , Sangki Hong , Chockalingam Ramasamy
发明人： Robert Patti , Sangki Hong , Chockalingam Ramasamy
IPC分类号： H01L21/50
CPC分类号： H01L23/544 , H01L21/76898 , H01L23/481 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2224/0401 , H01L2224/05572 , H01L2224/08145 , H01L2224/80895 , H01L2224/81121 , H01L2224/81203 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/12 , H01L2224/05552
摘要： A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial steeper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.
摘要翻译：公开了集成电路基板和其中使用的基板的堆叠方法。在该方法中，提供具有顶表面和底表面的集成电路基板。衬底被垂直分割成多个层，包括其中构成集成电路元件的集成电路层和与底表面相邻的缓冲层。构建从晶片的顶表面延伸到衬底到比电路层的深度更深的对准基准。通孔布置成当从基板的底表面观察时提供基准标记的图案。可以选择图案，使得当从所述晶片的所述背面观察时，其被商业陡峭/扫描仪/接触掩模对准器识别。在基板变薄之后，然后使用对准基准标记来定位在后续处理中使用的掩模。

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